PEB 3086 H V1.4 Infineon Technologies, PEB 3086 H V1.4 Datasheet - Page 214

• Manufacturer Part Number: PEB 3086 H V1.4
• Description: IC ISDN ACCESS CTRLR TQFP64
• Manufacturer: Infineon Technologies
• Series: ISAC™r

Specifications of PEB 3086 H V1.4

• Function: Subscriber Access Controller
• Interface: HDLC, IOM-2, ISDN, Parallel, SCI
• Number Of Circuits: 1
• Voltage - Supply: 3.3V
• Current - Supply: 30mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFQFP
• Includes: D-Channel Access Control and Priority Handler, Monitor Channel Handler, Non-Auto Mode, Transparent Mode
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEB3086HV1.4X; PEB3086HV14XP; SP000007567

CFS ... Configuration Select
This bit determines clock relations and recovery on S/T and IOM interfaces.
0: The IOM interface clock and frame signals are always active, "Power Down" state
included.
The states "Power Down" and "Power Up" are thus functionally identical except for the
indication: PD = 1111 and PU = 0111.
With the C/I command Timing (TIM) the microcontroller can enforce the "Power Up" state
and with C/I command Deactivation Indication (DI) the "Power Down" state is reached
again.
However, it is also possible to activate the S-interface directly with the C/I command
Activate Request (AR 8/10/L) without the TIM command.
1: The IOM interface clock and frame signals are normally inactive ("Power Down").
For activating the IOM-2 clocks the "Power Up" state can be induced by software
(IOM_CR.SPU) or by resetting CFS again.
After that the S-interface can be activated with the C/I command Activate Request (AR
8/10/L). The "Power Down" state can be reached again with the C/I command
Deactivation Indication (DI).
Note: After reset the IOM interface is always active. To reach the "Power Down" state
For general information please refer to
RSS2, RSS1... Reset Source Selection 2,1
The ISAC-SX reset sources for the RSTO output pin can be selected according to the
table below.
Bit 1
0
0
1
1
• If RSS = ’00’ no above listed reset source is selected and therefore no reset is
• Watchdog Timer
Data Sheet
generated at RSTO.
After the selection of the watchdog timer (RSS = ’11’) the timer is reset and started.
During every time period of 128 ms the microcontroller has to program the WTC1 and
WTC2 bits in two consecutive bit pattern (see description of the WTC1, 2 bits)
the CFS-bit has to be set.
RSS
Bit 0
0
1
0
1
C/I Code
Change
--
(reserved)
x
--
Chapter
214
3.3.9.
EAW
--
x
--
Detailed Register Description
Watchdog
Timer
--
--
x
PEB 3086
2003-01-30
ISAC-SX