BU2092 Rohm, BU2092 Datasheet
BU2092
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BU2092 Summary of contents
Page 1
... On the falling edge of the pulse, if the DATA pin is HIGH, the data in the shift register is output in parallel Q11. For the BU2092 / F / FV, shift data read at the rising edge of CLOCK is output in parallel Q11 at the rising edge of LCK. These ICs also have an OE pin, which when HIGH, forces data to be output, regardless of the shift data state. • ...
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... Standard ICs • Absolute maximum ratings (Ta = 25°C) (BU2090 / F / FS, BU2092 / F / FV) Parameter Symbol Power supply voltage BU2090 / Power dissipation BU2092 / BU2090 / Power dissipation BU2092 / Operating temperature Storage temperature Input voltage Output voltage 1 Unmounted 2 When mounted on a glass epoxy board of 50mm ...
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... CLOCK 3 Q10 14 12-bit storage register 1 LCK BU2092FV DATA 2 CLOCK 3 LCK BU2092 / BU2092F / BU2092FV 18 V Control circuit 12-bit shift register Q11 16 Q10 Output buffer (open drain Control circuit 12-bit shift register 18 Q11 12-bit storage register Q10 Output buffer (open drain N. ...
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... Parallel data output 12 N.C. Not connected 13 N.C. Not connected 14 Q7 Parallel data output 15 Q8 Parallel data output 16 Q9 Parallel data output 17 Q10 Parallel data output 18 Q11 Parallel data output 19 OE Output Enable 20 V Power supply DD BU2090 / BU2090F / BU2090FS / BU2092 / BU2092F / BU2092FV ...
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... W W 90% 90% 10% 10 LSUL LHL 90% 10% 10% Fig.1 BU2090 / BU2090F / BU2090FS / BU2092 / BU2092F / BU2092FV Unit V Conditions DD 5 — — 20mA 5mA 25. OUTPUT: OPEN ...
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... Standard ICs BU2092 / switching characteristics (unless otherwise noted 25°C, V Parameter Symbol t PLZ (LCK) Transmission delay time (LCK to OUTPUT QX) t PZL (LCK) t PLZ Output disable time (OE to OUTPUT QX) t PZL Minimum clock pulse width Minimum latch pulse width W (LCK) Setup time t S (LCK to CLOCK) ...
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... Contents of shift register are stored in storage register. No change in shift register Q11 output for the BU2090 / and BU2092 / Nch open drain output. When the shift register transfer data is LOW, the corresponding output FET is ON (continuous state). When the transfer data is HIGH, the output FET is OFF (discontinuous). ...
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... However, when the DATA pin is HIGH, the content of the 12-bit shift register is latched and is output to the corresponding Q0 to Q11. CLOCK DATA D11 D10 D9 D8 Q11 Q10 Note 1) Note 2) Pull-up resistance is connected to the output pin. Fig.3 Operation timing chart BU2090 / BU2090F / BU2090FS / BU2092 / BU2092F / BU2092FV indicates unstable output. ...
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... Standard ICs For the BU2092 / The content of the 12-bit shift register is stored in the 12-bit storage register at the rising edge of LCK, and is output to the corresponding Q0 to Q11. When OE is HIGH, regardless of the content of the storage register, the output FET turns OFF and enters a HIGH (discontinuous) state. ...
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... Standard ICs • Application example BU2090 / CLOCK DATA GND ( Control circuit BU2092 / F / (FV) GND (V ) DATA SS CLOCK Control circuit LCK 10 BU2090 / BU2090F / BU2090FS / BU2092 / BU2092F / BU2092FV V DD GND ( Fig GND ( Fig.6 LED power supply LED power supply ...
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... SOP18 (when mounted on a 50mm 50mm 1.6mm glass epoxy board) SOP18 (Unmounted) 400 SSOP-B20 (Unmounted) 200 150 100 AMBIENT TEMPERATURE Fig.8 BU2092 / thermal derating characteristics BU2090 / BU2090F / BU2090FS / BU2092 / BU2092F / BU2092FV 125 ...
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... SOP16 BU2090FS 6.6 0 0.8 0.36 0.1 SSOP-A16 12 BU2092 7. BU2092F 0.15 BU2092FV 0.3Min. 0.15 BU2090 / BU2090F / BU2090FS / BU2092 / BU2092F / BU2092FV 22 2.54 0.5 0.1 DIP18 11.2 0 1.27 0.4 0.1 0.3Min. 0.15 SOP18 6.5 6.5 0.2 0.2 20 ...