MC68HC705K1CS Freescale Semiconductor, Inc, MC68HC705K1CS Datasheet
MC68HC705K1CS
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MC68HC705K1CS Summary of contents
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... Freescale Semiconductor, Inc MC68HC705K1 HCMOS Microcontroller Unit For More Information On This Product, Go to: www.freescale.com MC68HC705K1/D Rev. 2.0 TECHNICAL DAT A ...
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... Freescale Semiconductor, Inc. Technical Data Technical Data For More Information On This Product, Go to: www.freescale.com MC68HC705K1 — Rev. 2.0 ...
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... Freescale Semiconductor, Inc. Technical Data — MC68HC705K1 Section 1. General Description . . . . . . . . . . . . . . . . . . . . 15 Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Section 3. Central Processor Unit (CPU Section 4. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Section 5. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Section 6. Low-Power Modes Section 7. Parallel Input/Output (I/O Section 8. Multifunction Timer . . . . . . . . . . . . . . . . . . . . . 75 Section 9. EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . 83 Section 10. Personality EPROM (PEPROM Section 11. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . 99 Section 12. Electrical Specifications . . . . . . . . . . . . . . . 117 Section 13 ...
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... Freescale Semiconductor, Inc. List of Sections Technical Data List of Sections For More Information On This Product, Go to: www.freescale.com MC68HC705K1 — Rev. 2.0 ...
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... Freescale Semiconductor, Inc. Technical Data — MC68HC705K1 1.1 1.2 1.3 1.4 1.5 1.6 1.6.1 1.6.2 1.6.2.1 1.6.2.2 1.6.2.3 1.6.2.4 1.6.2.5 1.6.3 1.6.4 1.6.5 1.6.6 2.1 2.2 2.3 2.4 2.5 MC68HC705K1 — Rev. 2.0 For More Information On This Product, Section 1. General Description Contents ...
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... Freescale Semiconductor, Inc. Table of Contents 2.6 2.7 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.4 4.1 4.2 4.3 4.3.1 4.3.2 4.3.2.1 4.3.2.2 4.3.2.3 4.3.3 4.3.3.1 4.3.3.2 4.4 5.1 5.2 Technical Data EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Personality EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . .30 Section 3. Central Processor Unit (CPU) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Introduction ...
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... Freescale Semiconductor, Inc. 5.3 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.4 5.4.1 5.4.2 5.4.3 5.4.4 6.1 6.2 6.3 6.4 6.5 6.6 7.1 7.2 7.3 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 MC68HC705K1 — Rev. 2.0 For More Information On This Product, Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Power-On Reset .52 External Reset ...
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... Freescale Semiconductor, Inc. Table of Contents 7.5 7.5.1 7.5.2 7.5.3 7.5.4 8.1 8.2 8.3 8.4 8.5 9.1 9.2 9.3 9.4 9.5 9.6 10.1 10.2 10.3 10.3.1 10.3.2 10.4 10.5 10.6 Technical Data Port .68 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Data Direction Register .70 Pulldown Register .70 Port B Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Section 8 ...
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... Freescale Semiconductor, Inc. 11.1 11.2 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.3.5 11.3.6 11.3.7 11.3.8 11.4 11.4.1 11.4.2 11.4.3 11.4.4 11.4.5 11.5 11.6 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 MC68HC705K1 — Rev. 2.0 For More Information On This Product, Section 11. Instruction Set Contents ...
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... Freescale Semiconductor, Inc. Table of Contents 12.9 12.10 5.0-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 12.11 3.3-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 12.12 Typical Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . .130 13.1 13.2 13.3 13.4 13.5 13.1 13.2 13.3 Technical Data 3.3-Volt DC Electrical Characteristics .122 Section 13. Mechanical Specifications Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 Plastic Dual In-Line Package (Case 648) ...
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... Freescale Semiconductor, Inc. Technical Data — MC68HC705K1 Figure 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1-9 2-1 2-2 3-1 3-2 3-3 3-4 3-5 3-6 4-1 4-2 4-3 4-4 5-1 5-2 6-1 MC68HC705K1 — Rev. 2.0 For More Information On This Product, Title MC68HC705K1 Block Diagram ...
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... Freescale Semiconductor, Inc. List of Figures Figure 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 8-1 8-2 8-3 8-4 9-1 9-2 9-3 10-1 10-2 10-3 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 12-10 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 12-11 2-Pin RC Oscillator R versus Frequency (V ...
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... Freescale Semiconductor, Inc. Technical Data — MC68HC705K1 Table 4-1 7-1 7-2 7-3 8-1 8-2 10-1 11-1 11-2 11-3 11-4 11-5 11-6 11-7 13-1 MC68HC705K1 — Rev. 2.0 For More Information On This Product, Title Reset/Interrupt Vector Addresses . . . . . . . . . . . . . . . . . . . . .48 Port A Pin Functions .68 PB0 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 PB1/OSC3 Pin Functions ...
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... Freescale Semiconductor, Inc. List of Tables Technical Data List of Tables For More Information On This Product, Go to: www.freescale.com MC68HC705K1 — Rev. 2.0 ...
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... Freescale Semiconductor, Inc. Technical Data — MC68HC705K1 1.1 Contents 1.2 1.3 1.4 1.5 1.6 1.6.1 1.6.2 1.6.2.1 1.6.2.2 1.6.2.3 1.6.2.4 1.6.2.5 1.6.3 1.6.4 1.6.5 1.6.6 1.2 Introduction The MC68HC705K1 is a member of the low-cost, high-performance M68HC05 Family of 8-bit microcontroller units (MCU). The M68HC05 Family is based on the customer-specified integrated circuit (CSIC) design strategy ...
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... Freescale Semiconductor, Inc. General Description On-chip memory of the MC68HC705K1 includes 504 bytes of erasable, programmable read-only memory (EPROM). In packages without the transparent window for EPROM erasure, the 504 EPROM bytes serve as one-time programmable read-only memory (OTPROM). 1.3 Features Features of the MCU include: • ...
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... Freescale Semiconductor, Inc. • • • 1.4 Mask Options These MC68HC705K1 options are programmable in the mask option register (MOR): • • • • • • • • The mask option register is an EPROM/OTPROM byte at location $0017. register and the EPROM/OTPROM programming procedure. ...
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... Freescale Semiconductor, Inc. General Description CPU CONTROL IRQ/V PP RESET RESET COP WATCHDOG AND ILLEGAL ADDRESS DETECT LOW-VOLTAGE V DD DETECT V SS OSC1 INTERNAL OSCILLATOR OSC2 Figure 1-1. MC68HC705K1 Block Diagram Technical Data USER EPROM/OTPROM 504 BYTES MASK OPTION REGISTER EPROM/OTPROM PERSONALITY EPROM/OTPROM ...
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... Freescale Semiconductor, Inc. 1.6 Pin Assignments Figure 1-2 1.6.1 V and and V DD from a single 5-volt power supply. Very fast signal transitions occur on the MCU pins, placing high short-duration current demands on the power supply. To prevent noise problems, take special care to provide good power supply bypassing at the MCU ...
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... Freescale Semiconductor, Inc. General Description 1.6.2 OSC1 and OSC2 The OSC1, OSC2, and PB1/OSC3 pins are the control connections for the 2-pin or 3-pin on-chip oscillator. The oscillator can be driven by any of these: • • • • The frequency of the internal oscillator is f internal oscillator output by two to produce the internal clock with a frequency ...
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... Freescale Semiconductor, Inc. NOTE: Use an AT-cut crystal and not a strip or tuning fork crystal. The MCU may overdrive or have the wrong characteristic impedance for a strip or tuning fork crystal. To use the crystal-driven oscillator, the RC and PIN3 bits in the mask option register must be clear. See the RC bit connects an internal 2-M startup resistor between OSC1 and OSC2 ...
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... Freescale Semiconductor, Inc. General Description To use the resonator-driven oscillator, the RC bit in the mask option register must be clear. See bit connects an internal 2-M startup resistor between OSC1 and OSC2. 1.6.2.3 2-Pin RC Oscillator For maximum cost reduction, use the 2-pin RC oscillator configuration shown in on OSC1 is a triangular wave ...
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... Freescale Semiconductor, Inc. disconnects the internal startup resistor. The PIN3 bit in the mask option register must remain erased (logic 0). The PIN3 bit selects the 3-pin RC oscillator configuration. See 1.6.2.4 3-Pin RC Oscillator Another low-cost option is the 3-pin RC oscillator configuration shown in Figure The OSC2 and PB1/OSC3 signals are square waves, and the signal on OSC1 is a triangular wave ...
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... Freescale Semiconductor, Inc. General Description 1.6.3 RESET A logic 0 on the RESET pin forces the MCU to a known startup state. See 1.6.4 IRQ/V PP The IRQ/V • • 1.6.5 PA7–PA0 PA7–PA0 are the pins of port A, a general-purpose, bidirectional I/O port. See 1 ...
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... Freescale Semiconductor, Inc. Technical Data — MC68HC705K1 2.1 Contents 2.2 2.3 2.4 2.5 2.6 2.7 2.2 Introduction This section describes the organization of the on-chip memory. 2.3 Memory Map The central processor unit (CPU) can address 1 Kbyte of memory space. The program counter typically advances one address at a time through the memory, reading the program instructions and data ...
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... Freescale Semiconductor, Inc. Memory 2.4 Input/Output Section The first 32 addresses of the memory space, $0001–$001F, are the I/O section. These are the addresses of the I/O control registers, status registers, and data registers. See 2.5 Random-Access Memory (RAM) The 32 addresses from $00E0 to $00FF serve as both the user RAM and the stack RAM ...
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... Freescale Semiconductor, Inc. $0000 I/O REGISTERS 32 BYTES $001F $0020 UNUSED 192 BYTES $00DF $00E0 USER STACK RAM RAM 32 BYTES 32 BYTES $00FF $0100 UNUSED 256 BYTES $01FF $0200 USER EPROM 496 BYTES $03EF $03F0 TEST ROM AND COP REGISTER (8 BYTES) $03F7 $03F8 ...
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... Freescale Semiconductor, Inc. Memory Addr. Register Name Port A Data Register $0000 (PORTA) See page 64. Reset: Port B Data Register $0001 (PORTB) See page 69. Reset: $0002 Unimplemented $0003 Unimplemented Data Direction Register A $0004 (DDRA) See page 65. Reset: Data Direction Register B $0005 (DDRB) See page 70. ...
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... Freescale Semiconductor, Inc. Addr. Register Name $000B Unimplemented $000D Unimplemented Read: PEPROM Bit Select Register $000E (PEBSR) Write: See page 93. Reset: Read: PEDATA PEPROM Status and Control $000F Register (PESCR) Write: See page 95. Reset: Read: Pulldown Register A $0010 (PDRA) Write: PDIA7 See page 66 ...
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... Freescale Semiconductor, Inc. Memory Addr. Register Name $0019 Unimplemented $001E Unimplemented $001F Test Register Reset: COP Register $03F0 (COPR) See page 54. Reset: Figure 2-2. I/O Register Summary (Sheet 2.6 EPROM/OTPROM An MCU with a quartz window has 504 bytes of erasable, programmable ROM (EPROM). The quartz window allows EPROM erasure with ultraviolet light ...
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... Freescale Semiconductor, Inc. Technical Data — MC68HC705K1 Section 3. Central Processor Unit (CPU) 3.1 Contents 3.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.4 3.2 Introduction This section describes the central processor unit (CPU) registers. MC68HC705K1 — Rev. 2.0 For More Information On This Product, Introduction ...
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... Freescale Semiconductor, Inc. Central Processor Unit (CPU) 3.3 CPU Registers Figure 3-1 of the memory map Technical Data shows the five CPU registers. CPU registers and are not part HALF-CARRY FLAG INTERRUPT MASK NEGATIVE FLAG ZERO FLAG CARRY/BORROW FLAG Figure 3-1. Programming Model ...
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... Freescale Semiconductor, Inc. 3.3.1 Accumulator The accumulator (A) shown in register. The CPU uses the accumulator to hold operands and results of arithmetic and non-arithmetic operations. Read: Write: Reset: 3.3.2 Index Register In the indexed addressing modes, the CPU uses the byte in the index register (X) shown in the operand ...
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... Freescale Semiconductor, Inc. Central Processor Unit (CPU) 3.3.3 Stack Pointer The stack pointer (SP) shown in contains the address of the next free location on the stack. During a reset or after the reset stack pointer (RSP) instruction, the stack pointer initializes to $00FF. The address in the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack ...
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... Freescale Semiconductor, Inc. 3.3.4 Program Counter The program counter (PC) shown in contains the address of the next instruction or operand to be fetched. The six most significant bits of the program counter are ignored internally and appear as 000000. Normally, the address in the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched ...
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... Freescale Semiconductor, Inc. Central Processor Unit (CPU) 3.3.5 Condition Code Register The condition code register (CCR) shown in register whose three most significant bits are permanently fixed at 111. The condition code register contains the interrupt mask and four flags that indicate the results of prior instructions. ...
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... Freescale Semiconductor, Inc. N — Negative Flag The CPU sets the negative flag when an arithmetic operation, logical operation, or data manipulation produces a negative result (bit 7 in the results is a logic 1). Reset has no effect on the negative flag. Z — Zero Flag The CPU sets the zero flag when an arithmetic operation, logical operation, or data manipulation produces a result of $00 ...
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... Freescale Semiconductor, Inc. Central Processor Unit (CPU) Technical Data Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com MC68HC705K1 — Rev. 2.0 ...
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... Freescale Semiconductor, Inc. Technical Data — MC68HC705K1 4.1 Contents 4.2 4.3 4.3.1 4.3.2 4.3.2.1 4.3.2.2 4.3.2.3 4.3.3 4.3.3.1 4.3.3.2 4.4 4.2 Introduction This section describes how interrupts temporarily change the normal processing sequence. MC68HC705K1 — Rev. 2.0 For More Information On This Product, Section 4 ...
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... Freescale Semiconductor, Inc. Interrupts 4.3 Interrupt Types These conditions generate interrupts: • • • • • An interrupt temporarily stops normal program execution to process a particular event. An interrupt does not stop the execution of the instruction in progress, but takes effect when the current instruction completes its execution ...
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... Freescale Semiconductor, Inc. 4.3.2.1 IRQ/V Pin PP An interrupt signal on the IRQ/V request. After completing the current instruction, the CPU tests these bits: • • • If both the IRQ latch and the IRQE bit are set, and the I bit is clear, the CPU then begins the interrupt sequence. The CPU clears the IRQ latch while it fetches the interrupt vector, so that another external interrupt request can be latched during the interrupt service routine ...
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... Freescale Semiconductor, Inc. Interrupts Programming the LEVEL bit to a logic 0 selects the edge-sensitive-only trigger option. When LEVEL = 0: • • NOTE: If the IRQ/V IRQ/V PP PA3 PA2 PA1 PA0 MASK OPTION REGISTER Technical Data A falling edge on the IRQ/V PP request. A subsequent interrupt request can be latched only after the ...
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... Freescale Semiconductor, Inc. 4.3.2.2 PA3–PA0 Pins Programming the PIRQ bit in the mask option register to a logic 1 enables pins PA3–PA0 to serve as additional external interrupt sources. See 9.6 Mask Option latches an external interrupt request. After completing the current instruction, the CPU tests these bits: • ...
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... Freescale Semiconductor, Inc. Interrupts Programming the LEVEL bit to a logic 0 selects the edge-sensitive only trigger option. When LEVEL = 0: • • • • Technical Data A rising edge on a PA3–PA0 pin latches an external interrupt request if and only if all other PA3–PA0 pins are low and the IRQ/V pin is high ...
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... Freescale Semiconductor, Inc. 4.3.2.3 IRQ Status and Control Register The IRQ status and control register (ISCR) contains an external interrupt mask, an external interrupt flag, and a flag reset bit. Unused bits read as logic 0s. Address: Read: Write: Reset: IRQE — External Interrupt Request Enable Bit This read/write bit enables external interrupts ...
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... Freescale Semiconductor, Inc. Interrupts IRQR — Interrupt Request Reset Bit Writing a logic 1 to this write-only bit clears the IRQF bit. Writing a logic 0 to IRQR has no effect. Reset has no effect on IRQR. 4.3.3 Timer Interrupts The multifunction timer can generate these interrupts: • ...
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... Freescale Semiconductor, Inc. 4.4 Interrupt Processing The CPU does these things to begin servicing an interrupt: • • • The return-from-interrupt (RTI) instruction causes the CPU to recover the CPU registers from the stack as shown in UNSTACKING ORDER STACKING ORDER Figure 4-3. Interrupt Stacking Order MC68HC705K1 — ...
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... Freescale Semiconductor, Inc. Interrupts Table 4-1 assignments. Table 4-1. Reset/Interrupt Vector Addresses Function Source Power-on logic RESET pin COP watchdog Reset Low voltage detect Illegal address logic Software interrupt User code (SWI) IRQ/V pin PP PA3 pin External PA2 pin interrupts PA1 pin ...
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... Freescale Semiconductor, Inc. Figure 4-4 MC68HC705K1 — Rev. 2.0 For More Information On This Product, shows the sequence of events caused by an interrupt. FROM RESET YES I BIT SET? NO YES EXTERNAL INTERRUPT? NO YES TIMER INTERRUPT? STACK PCL, PCH CCR NO LOAD PC WITH INTERRUPT VECTOR FETCH NEXT ...
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... Freescale Semiconductor, Inc. Interrupts Technical Data Interrupts For More Information On This Product, Go to: www.freescale.com MC68HC705K1 — Rev. 2.0 ...
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... Freescale Semiconductor, Inc. Technical Data — MC68HC705K1 5.1 Contents 5.3 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.4 5.4.1 5.4.2 5.4.3 5.4.4 5.2 Introduction This section describes the five reset sources and how they initialize the microcontroller unit (MCU). MC68HC705K1 — Rev. 2.0 For More Information On This Product, Reset Types ...
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... Freescale Semiconductor, Inc. Resets 5.3 Reset Types A reset immediately stops the operation of the instruction being executed, initializes certain control bits, and loads the program counter with a user-defined reset vector address. These conditions produce a reset: • • • • • 5.3.1 Power-On Reset ...
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... Freescale Semiconductor, Inc. MASK OPTION REGISTER COP WATCHDOG LOW-VOLTAGE RESET IRQ/V PP POWER-ON RESET ILLEGAL ADDRESS RESET INTERNAL ADDRESS BUS RESET NOTE: To avoid overloading some power supply designs, do not connect the RESET pin directly to V MC68HC705K1 — Rev. 2.0 For More Information On This Product, ...
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... Freescale Semiconductor, Inc. Resets 5.3.3 Computer Operating Properly (COP) Reset A timeout of the COP watchdog generates a COP reset. The COP watchdog is part of a software error detection system and must be cleared periodically to start a new timeout period. (See Watchdog.) To clear the COP watchdog and prevent a COP reset, write a logic 0 to bit 0 (COPC) of the COP register at location $03F0 ...
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... Freescale Semiconductor, Inc. 5.3.5 Low-Voltage Reset The low-voltage reset circuit generates a reset signal if the voltage on the V DD while the low-voltage reset circuit is enabled. Programming the LVRE bit to a logic 1 enables the low-voltage reset function. When erased, the LVRE bit in the mask option register disables the low-voltage reset circuit ...
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... Freescale Semiconductor, Inc. Resets 5.4.2 I/O Port Registers A reset has these effects on input/output (I/O) port registers: • • • • • 5.4.3 Multifunction Timer A reset has these effects on the multifunction timer: • • 5.4.4 COP Watchdog A reset clears the COP watchdog timeout counter. ...
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... Freescale Semiconductor, Inc. Technical Data — MC68HC705K1 6.1 Contents 6.2 6.3 6.4 6.5 6.6 6.2 Introduction This section describes the four low-power modes: • • • • 6.3 Stop Mode If the SWAIT bit in the mask option register (MOR) is programmed to a logic 0, the STOP instruction puts the microcontroller unit (MCU) in its lowest power-consumption mode and has these effects on the MCU: • ...
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... Freescale Semiconductor, Inc. Low-Power Modes • • • The STOP instruction does not affect any other registers or any input/output (I/O) lines. These conditions bring the MCU out of stop mode: • • • When the MCU exits stop mode, processing resumes after a stabilization delay of 4064 oscillator cycles ...
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... Freescale Semiconductor, Inc. These conditions restart the CPU clock and bring the MCU out of wait mode: • • • • • 6.5 Halt Mode The STOP instruction puts the MCU in halt mode if the SWAIT bit in the mask option register is programmed to a logic 1. Halt mode is identical to wait mode, except that a recovery delay of 1– ...
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... Freescale Semiconductor, Inc. Low-Power Modes STOP SWAIT BIT SET? NO CLEAR I BIT IN CCR SET IRQE BIT IN ISCR CLEAR TOF, RTIF, TOIE, AND RTIE BITS IN TSCR TURN OFF INTERNAL OSCILLATOR YES EXTERNAL RESET? NO YES EXTERNAL INTERRUPT? NO TURN ON INTERNAL OSCILLATOR RESET STABILIZATION TIMER END OF ...
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... Freescale Semiconductor, Inc. 6.6 Data-Retention Mode In data-retention mode, the MCU retains random-access memory (RAM) contents and CPU register contents at V Data-retention mode allows the MCU to remain in a low power-consumption state during which it retains data, but the CPU cannot execute instructions. To put the MCU in data-retention mode: 1 ...
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... Freescale Semiconductor, Inc. Low-Power Modes Technical Data Low-Power Modes For More Information On This Product, Go to: www.freescale.com MC68HC705K1 — Rev. 2.0 ...
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... Freescale Semiconductor, Inc. Technical Data — MC68HC705K1 7.1 Contents 7.2 7.3 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.5 7.5.1 7.5.2 7.5.3 7.5.4 7.2 Introduction This section describes the two bidirectional input/output (I/O) ports: • • MC68HC705K1 — Rev. 2.0 For More Information On This Product, Section 7 ...
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... Freescale Semiconductor, Inc. Parallel Input/Output (I/O) 7.3 I/O Port Function The 10 bidirectional input/output (I/O) pins form two parallel I/O ports. Each I/O pin is programmable as an input or an output. The contents of the data direction registers determine the data direction of each I/O pin. ...
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... Freescale Semiconductor, Inc. 7.4.2 Data Direction Register A The contents of data direction register A (DDRA) determine whether each port A pin is an input or an output. Writing a logic DDRA bit enables the output buffer for the associated port A pin; a logic 0 disables the output buffer. A reset initializes all DDRA bits to logic 0s, configuring all port A pins as inputs ...
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... Freescale Semiconductor, Inc. Parallel Input/Output (I/O) 7.4.3 Pulldown Register A Programming the SWPDI bit in the mask option register to a logic 0 enables the port A and port B pulldown devices. The port A pulldown devices sink approximately 100 A and are under the control of the PDIA7–PDIA0 bits in pulldown register A (PDRA). ...
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... Freescale Semiconductor, Inc. 7.4.4 Port A External Interrupts Programming the PIRQ bit in the mask option register to a logic 1 enables the PA3–PA0 pins to serve as external interrupt pins in addition to the IRQ/V logic rising edge. The active interrupt state for the IRQ/V a logic falling edge. The state of the LEVEL bit in the mask option register determines whether external interrupt inputs are edge-sensitive only or both edge- and level-sensitive ...
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... Freescale Semiconductor, Inc. Parallel Input/Output (I/O) When a port A pin is programmed as an output, reading the port bit actually reads the value of the data latch and not the voltage on the pin itself. When a port A pin is programmed as an input, reading the port bit reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction register bit ...
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... Freescale Semiconductor, Inc. is programmed input, reading the port B data register returns the logic state of the pin. Reset has no effect on port B data. Address: Read: Write: Reset: PB1/OSC3 — Port B Data Bit 1/Oscillator Output Bit This read/write data bit is software programmable. Data direction of PB1 bit is under the control of the DDRB1 bit in data direction register B ...
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... Freescale Semiconductor, Inc. Parallel Input/Output (I/O) 7.5.2 Data Direction Register B The contents of data direction register B (DDRB) determine whether each port B pin is an input or an output. Writing a logic DDRB bit enables the output buffer for the associated port B pin; a logic 0 disables the output buffer. A reset initializes all DDRB bits to logic 0, configuring all port B pins as inputs ...
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... Freescale Semiconductor, Inc. Programming the SWPDI bit to a logic 1 disables both of the port B pulldown devices. Reset initializes both port B pins as inputs with pulldown devices disabled when the SWPDI bit is programmed to a logic 1. Address: Read: Write: Reset: PDIB1 and PDIB0 — Port B Pulldown Inhibit Bits 1 and 0 Writing logic 0s to these write-only bits turns on the port B pulldown devices ...
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... Freescale Semiconductor, Inc. Parallel Input/Output (I/O) READ $0005 WRITE $0005 WRITE $0001 READ $0001 WRITE $0011 READ $0005 WRITE $0005 WRITE $0001 READ $0001 WRITE $0011 RESET Technical Data DATA DIRECTION REGISTER B BIT DDRB1 PORT B DATA REGISTER BIT PB1 PULLDOWN REGISTER B ...
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... Freescale Semiconductor, Inc. When a port B pin is programmed as an output, reading the port bit reads the value of the data latch and not the voltage on the pin itself. When a port B pin is programmed as an input, reading the port bit reads the voltage level on the pin. The data latch can always be written, regardless of the state of its DDR bit ...
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... Freescale Semiconductor, Inc. Parallel Input/Output (I/O) Control Bits RC PIN3 SWPDI PDIB1 ( Don’t care Undefined Technical Data Table 7-3. PB1/OSC3 Pin Functions Accesses PB1/OSC3 to PDRB Pin Mode DDRB1 Read (2) 0 Input, hi Output U Input pulldown on 1 Output U 0 Input, hi Output U 0 Input, hi-z ...
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... Freescale Semiconductor, Inc. Technical Data — MC68HC705K1 8.1 Contents 8.2 8.3 8.4 8.5 8.2 Introduction This section describes the operation of the multifunction timer and the computer operating properly (COP) watchdog. organization of the timer subsystem. MC68HC705K1 — Rev. 2.0 For More Information On This Product, Section 8 ...
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... Freescale Semiconductor, Inc. Multifunction Timer OVERFLOW 2 RESET Figure 8-1. Multifunction Timer Block Diagram Technical Data TIMER COUNTER REGISTER BITS 0–7 OF 15-STAGE RIPPLE COUNTER RESET TIMER STATUS/CONTROL REGISTER RTI RATE SELECT BITS 8–14 OF 15-STAGE RIPPLE COUNTER Multifunction Timer For More Information On This Product, Go to: www ...
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... Freescale Semiconductor, Inc. 8.3 Timer Status and Control Register The read/write timer status and control register (TSCR) contains these bits: • • • • Address: Read: Write: Reset: TOF — Timer Overflow Flag This read-only flag becomes set when the first eight stages of the counter roll over from $FF to $00 ...
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... Freescale Semiconductor, Inc. Multifunction Timer RTIE — Real-Time Interrupt Enable Bit This read/write bit enables real-time interrupts. Reset clears RTIE. TOFR — Timer Overflow Flag Reset Writing a logic 1 to this write-only bit clears the TOF bit. TOFR always reads as a logic 0. Reset does not affect TOFR. ...
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... Freescale Semiconductor, Inc. 8.4 Timer Counter Register A 15-stage ripple counter is the core of the timer. The value of the first eight stages is readable at any time from the read-only timer counter register (TCNTR). Address: Read: Write: Reset: Power-on clears the entire counter chain and begins clocking the counter ...
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... Freescale Semiconductor, Inc. Multifunction Timer 8.5 COP Watchdog Four counter stages at the end of the timer make up the mask-optional computer operating properly (COP) watchdog. The COP watchdog is a software error detection system that automatically times out and resets the MCU if not cleared periodically by a program sequence. Writing a logic 0 to bit 0 of the COP register clears the COP watchdog and prevents a COP reset ...
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... Freescale Semiconductor, Inc. Table 8-2 disabling the COP watchdog. Voltage on IRQ/V Less than 2 Less than 2 Less than 2 More than 2 1. The SWAIT bit in the mask option register converts STOP instructions to HALT instruc- tions. 2. Reset the COP watchdog immediately before executing the WAIT/HALT instruction. ...
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... Freescale Semiconductor, Inc. Multifunction Timer Technical Data Multifunction Timer For More Information On This Product, Go to: www.freescale.com MC68HC705K1 — Rev. 2.0 ...
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... Freescale Semiconductor, Inc. Technical Data — MC68HC705K1 9.1 Contents 9.2 9.3 9.4 9.5 9.6 9.2 Introduction This section describes how to program the 504-byte erasable, programmable read-only memory (EPROM)/one-time programmable read-only memory (OTPROM). NOTE: In packages with no quartz window, the 504 bytes of EPROM function as an OTPROM. MC68HC705K1 — ...
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... Freescale Semiconductor, Inc. EPROM/OTPROM 9.3 EPROM Programming Register The EPROM programming register (EPROG) contains the control bits for programming the EPROM/OTPROM. In normal operation, the EPROM programming register is a read-only register that contains all logic 0s. Address: Read: Write: Reset: ELAT — EPROM Bus Latch Bit This read/write bit configures address and data buses for programming the EPROM/OTPROM array ...
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... Freescale Semiconductor, Inc. NOTE: Writing logic 1s to both the ELAT and EPGM bits with a single instruction sets ELAT and clears EPGM. ELAT must be set first by a separate instruction. Bits 7–3 — Reserved Bits 7–3 are factory test bits that always read as logic 0s. ...
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... Freescale Semiconductor, Inc. EPROM/OTPROM 1 STROBE INIT ACK 0 4 100 0.1 F 100 Technical Data 2 2.2 k MC68HC705K1 1 RESET 2 PB1 3 PB0 4 IRQ PA0 6 PA1 7 PA2 8 PA3 DIP SOCKET MC68HC705K1 1 RESET 2 PB1 3 PB0 4 IRQ PA0 6 PA1 7 PA2 8 PA3 SOIC SOCKET 170 H 330 8 DR COL SW COL ...
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... Freescale Semiconductor, Inc. 9.5 EPROM Erasing MCUs with windowed packages permit EPROM erasure with ultraviolet light. Erase the EPROM by exposing Ws/cm with a wave length of 2537 angstroms. Position the ultraviolet light source 1 inch from the window. Do not use a shortwave filter. The erased state of an EPROM bit is a logic 0 ...
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... Freescale Semiconductor, Inc. EPROM/OTPROM SWPDI —Software Pulldown Inhibit Bit This EPROM bit inhibits software control of the port A and port B pulldown devices. PIN3 — 3-Pin RC Oscillator Bit This EPROM bit configures the on-chip oscillator as either a 3-pin oscillator 2-pin oscillator. The PIN3 bit should be cleared when the RC bit is clear. RC — ...
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... Freescale Semiconductor, Inc. PIRQ — Port A IRQ Enable Bit This EPROM bit enables the PA3–PA0 pins to function as external interrupt sources. LEVEL — External Interrupt Sensitivity Bit This EPROM bit makes the external interrupt inputs level-triggered as well as edge-triggered. COPEN — COP Watchdog Enable Bit This EPROM bit enables the COP watchdog ...
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... Freescale Semiconductor, Inc. EPROM/OTPROM Technical Data EPROM/OTPROM For More Information On This Product, Go to: www.freescale.com MC68HC705K1 — Rev. 2.0 ...
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... Freescale Semiconductor, Inc. Technical Data — MC68HC705K1 Section 10. Personality EPROM (PEPROM) 10.1 Contents 10.2 10.3 10.3.1 10.3.2 10.4 10.5 10.6 10.2 Introduction This section describes how to program the 64-bit personality erasable, programmable read-only memory (PEPROM). structure of the PEPROM subsystem. MC68HC705K1 — Rev. 2.0 For More Information On This Product, Introduction ...
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... Freescale Semiconductor, Inc. Personality EPROM (PEPROM) INTERNAL DATA BUS PEPROM STATUS/CONTROL REGISTER SINGLE SENSE AMPLIFIER 8-TO-1 COLUMN DECODER V SWITCH PP PEPROM STATUS/CONTROL REGISTER INTERNAL DATA BUS Technical Data RESET V PP ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 8-TO-1 ROW DECODER AND MULTIPLEXER ...
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... Freescale Semiconductor, Inc. 10.3 PEPROM Registers Two input/output (I/O) registers control programming and reading of the PEPROM: • • 10.3.1 PEPROM Bit Select Register The PEPROM bit select register (PEBSR) selects one of 64 bits in the PEPROM array. Reset clears all the bits in the PEPROM bit select register ...
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... Freescale Semiconductor, Inc. Personality EPROM (PEPROM) Technical Data Table 10-1. PEPROM Bit Selection PEBSR PEPROM Bit Selected $00 Row 0 $01 Row 1 $02 Row 2 $07 Row 7 $08 Row 0 $09 Row 1 $0A Row 2 $0F Row 7 $10 Row 0 $11 Row 1 $12 Row 2 $37 Row 7 $38 ...
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... Freescale Semiconductor, Inc. 10.3.2 PEPROM Status and Control Register The PEPROM status and control register (PESCR) controls the PEPROM programming voltage. This register also transfers the PEPROM bits to the internal data bus and contains a row zero flag. Address: Read: PEDATA Write: Reset: Figure 10-3 ...
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... Freescale Semiconductor, Inc. Personality EPROM (PEPROM) 10.4 PEPROM Programming Factory-provided software for programming the PEPROM is available through the Motorola web site at: htt://mcu.motsps.com The circuit shown in program the PEPROM with the factory-provided programming software. NOTE: To program the PEPROM, V The PEPROM can also be programmed by user software with V ...
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... Freescale Semiconductor, Inc. Reading the PEPROM is easiest when each PEPROM column contains one byte. Selecting a row 0 bit selects the first bit, and incrementing the PEPROM bit select register (PEBSR) selects the next row 1 bit from the same column. Incrementing PEBSR seven more times selects the remaining bits of the column and selects the row 0 bit of the next column, setting the row 0 flag, PEPRZF ...
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... Freescale Semiconductor, Inc. Personality EPROM (PEPROM) Technical Data Personality EPROM (PEPROM) For More Information On This Product, Go to: www.freescale.com MC68HC705K1 — Rev. 2.0 ...
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... Freescale Semiconductor, Inc. Technical Data — MC68HC705K1 11.1 Contents 11.2 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.3.5 11.3.6 11.3.7 11.3.8 11.4 11.4.1 11.4.2 11.4.3 11.4.4 11.4.5 11.5 11.6 MC68HC705K1 — Rev. 2.0 For More Information On This Product, Section 11. Instruction Set Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Addressing Modes ...
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... Freescale Semiconductor, Inc. Instruction Set 11.2 Introduction The microcontroller unit (MCU) instruction set has 62 instructions and uses eight addressing modes. The instructions include all those of the M146805 CMOS Family plus one more: the unsigned multiply (MUL) instruction. The MUL instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X) ...
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... Freescale Semiconductor, Inc. 11.3.1 Inherent Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no operand address and are one byte long ...
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... Freescale Semiconductor, Inc. Instruction Set 11.3.5 Indexed, No Offset Indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. The index register contains the low byte of the effective address of the operand. The CPU automatically uses $00 as the high byte, so these instructions can address locations $0000– ...
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... Freescale Semiconductor, Inc. 11.3.8 Relative Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed, two’ ...
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... Freescale Semiconductor, Inc. Instruction Set 11.4.1 Register/Memory Instructions These instructions operate on CPU registers and memory locations. Most of them use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. Technical Data Table 11-1. Register/Memory Instructions ...
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... Freescale Semiconductor, Inc. 11.4.2 Read-Modify-Write Instructions These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. NOTE: Do not use read-modify-write operations on write-only registers. MC68HC705K1 — Rev. 2.0 For More Information On This Product, Table 11-2 ...
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... Freescale Semiconductor, Inc. Instruction Set 11.4.3 Jump/Branch Instructions Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met ...
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... Freescale Semiconductor, Inc. MC68HC705K1 — Rev. 2.0 For More Information On This Product, Table 11-3. Jump and Branch Instructions Instruction Branch if carry bit clear Branch if carry bit set Branch if equal Branch if half-carry bit clear Branch if half-carry bit set Branch if higher Branch if higher or same ...
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... Freescale Semiconductor, Inc. Instruction Set 11.4.4 Bit Manipulation Instructions The CPU can set or clear any writable bit in the first 256 bytes of memory, which includes I/O registers and on-chip RAM locations. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations ...
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... Freescale Semiconductor, Inc. 11.4.5 Control Instructions These instructions act on CPU registers and control CPU operation during program execution. MC68HC705K1 — Rev. 2.0 For More Information On This Product, Table 11-5. Control Instructions Instruction Clear carry bit Clear interrupt mask No operation Reset stack pointer ...
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... Freescale Semiconductor, Inc. Instruction Set 11.5 Instruction Set Summary Table 11-6. Instruction Set Summary (Sheet Source Operation Form ADC #opr ADC opr ADC opr Add with Carry ADC opr,X ADC opr,X ADC ,X ADD #opr ADD opr ADD opr Add without Carry ...
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... Freescale Semiconductor, Inc. Table 11-6. Instruction Set Summary (Sheet Source Operation Form BIH rel Branch if IRQ Pin High BIL rel Branch if IRQ Pin Low BIT #opr BIT opr BIT opr Bit Test Accumulator with Memory Byte BIT opr,X BIT opr,X BIT ,X ...
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... Freescale Semiconductor, Inc. Instruction Set Table 11-6. Instruction Set Summary (Sheet Source Operation Form CLR opr CLRA CLRX Clear Byte CLR opr,X CLR ,X CMP #opr CMP opr CMP opr Compare Accumulator with Memory Byte CMP opr,X CMP opr,X CMP ,X COM opr ...
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... Freescale Semiconductor, Inc. Table 11-6. Instruction Set Summary (Sheet Source Operation Form JSR opr JSR opr JSR opr,X Jump to Subroutine JSR opr,X JSR ,X LDA #opr LDA opr LDA opr Load Accumulator with Memory Byte LDA opr,X LDA opr,X LDA ,X LDX #opr ...
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... Freescale Semiconductor, Inc. Instruction Set Table 11-6. Instruction Set Summary (Sheet Source Operation Form ROR opr RORA RORX Rotate Byte Right through Carry Bit ROR opr,X ROR ,X RSP Reset Stack Pointer RTI Return from Interrupt RTS Return from Subroutine SBC #opr ...
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... Freescale Semiconductor, Inc. Table 11-6. Instruction Set Summary (Sheet Source Operation Form TST opr TSTA TSTX Test Memory Byte for Negative or Zero TST opr,X TST ,X TXA Transfer Index Register to Accumulator WAIT Stop CPU Clock and Enable Interrupts A Accumulator C Carry/borrow flag CCR ...
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... Freescale Semiconductor, Inc. Instruction Set Technical Data Instruction Set For More Information On This Product, Go to: www.freescale.com MC68HC705K1 — Rev. 2.0 ...
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... Freescale Semiconductor, Inc. Technical Data — MC68HC705K1 12.1 Contents 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10 5.0-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 12.11 3.3-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 12.12 Typical Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . .130 12.2 Introduction This section contains electrical and timing specifications. ...
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... Freescale Semiconductor, Inc. Electrical Specifications 12.3 Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. The MCU contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table here ...
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... Freescale Semiconductor, Inc. 12.5 Thermal Characteristics Maximum junction temperature Thermal resistance MC68HC705K1P MC68HC705K1DW Plastic dual in-line package (PDIP Small outline integrated circuit (SOIC) 12.6 Power Considerations The average chip junction temperature, T Where INT P I/O For most applications, P Ignoring P Solving equations (1) and (2) for K gives: where constant pertaining to the particular part ...
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... Freescale Semiconductor, Inc. Electrical Specifications 12.7 Equivalent Pin Loading Figure 12-1 purposes. Technical Data shows the equivalent input/output (I/O) pin loading for test TEST POINT C R1 PINS PA3–PA0, PB1–PB0 PA7–PA4 PA3–PA0, PB1–PB0 Figure 12-1. Equivalent Test Load ...
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... Freescale Semiconductor, Inc. 12.8 5.0-Volt DC Electrical Characteristics Characteristic Output voltage I 10.0 A Load I –10.0 A Load Output high voltage –0.8 mA Load PA7–PA0, PB1/OSC3, PB0 Output low voltage I = 1.6 mA, PA3–PA0, PB1/OSC3, PB0 Load I = 8.0 mA, PC7–PC4 Load Input high voltage PA7–PA0, PB1/OSC3, PB0, IRQ/V Input low voltage PA7– ...
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... Freescale Semiconductor, Inc. Electrical Specifications 12.9 3.3-Volt DC Electrical Characteristics Characteristic Output voltage I 10.0 A Load I –10.0 A Load Output high voltage –0.4 mA Load PA7–PA0, PB1/OSC3, PB0 Output low voltage I = 0.4 mA, PA3–PA0, PB1/OSC3, PB0 Load I = 3.0 mA, PC7–PC4 Load Input high voltage PA7– ...
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... Freescale Semiconductor, Inc 5 0.8 (NOTE 2) 0.7 0.6 0.5 0.4 0.3 0.2 0 –1.0 –2.0 I (mA) OH Notes: 1. Shaded area indicates variation in driver characteristics due to changes in temperature and for normal processing tolerances. Within the limited range of values shown, V versus I curves are approximately straight lines. ...
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... Freescale Semiconductor, Inc. Electrical Specifications Technical Data 3.0 2.5 5.5 V 4.5 V 2.0 3.6 V 3.0 V 1.5 1.0 0 0.5 INTERNAL CLOCK FREQUENCY (MHz) Figure 12-4. Run I versus Internal Clock Frequency DD 900 800 700 5.5 V 4.5 V 600 3.6 V 500 3.0 V 400 300 200 ...
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... Freescale Semiconductor, Inc. MC68HC705K1 — Rev. 2.0 For More Information On This Product, 3.3-Volt DC Electrical Characteristics 2500 2000 5.5 V 4.5 V 1500 3.6 V 3.0 V 1000 500 TEMPERATURE ( C) Figure 12-6. Stop I versus Temperature DD Electrical Specifications Go to: www.freescale.com Electrical Specifications 60 80 100 Technical Data ...
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... Freescale Semiconductor, Inc. Electrical Specifications 12.10 5.0-Volt Control Timing Characteristic Oscillator frequency 3-pin RC oscillator 2-pin RC oscillator (2) Crystal/ceramic resonator External clock Internal operating frequency (f OSC 3-pin RC oscillator 2-pin RC oscillator Crystal/ceramic resonator External clock 2-pin RC oscillator frequency combined stability f = 2.0 MHz 5.0 Vdc 10%; T ...
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... Freescale Semiconductor, Inc. 12.11 3.3-Volt Control Timing Characteristic Oscillator frequency 3-pin RC oscillator 2-pin RC oscillator (2) Crystal/ceramic resonator External clock Internal operating frequency (f OSC 3-pin RC oscillator 2-pin RC oscillator Crystal/ceramic resonator External clock 2-pin RC oscillator frequency combined stability f = 2.0 MHz 3.3 Vdc 10%; T OSC ...
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... Freescale Semiconductor, Inc. Electrical Specifications IRQ/V PIN PP IRQ IRQ n IRQ (INTERNAL) Figure 12-7. External Interrupt Timing OSC (NOTE RESET t ILIH IRQ/V (NOTE 2) PP IRQ/V (NOTE 3) PP INTERNAL CLOCK INTERNAL ADDRESS BUS Notes: 1. Internal clocking from OSC1 pin. 2. Edge-triggered external interrupt mask option. ...
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... Freescale Semiconductor, Inc (NOTE 1) OSC1 PIN INTERNAL CLOCK INTERNAL ADDRESS BUS INTERNAL DATA BUS Notes: 1. Power-on reset threshold is typically between 1 V and Internal clock, internal address bus, and internal data bus are not available externally. Figure 12-9. Power-On Reset Timing INTERNAL ...
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... Freescale Semiconductor, Inc. Electrical Specifications 12.12 Typical Oscillator Characteristics Oscillator Type 2-pin RC oscillator 3-pin RC oscillator 2-pin RC oscillator 3-pin RC oscillator 2-pin RC oscillator 3-pin RC oscillator 2-pin RC oscillator 3-pin RC oscillator 1. V Technical Data Parameter Nominal Frequency Frequency Variation (Part-to-Part) 2 MHz 1 MHz Frequency Variation ...
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... Freescale Semiconductor, Inc. Figure 12-11. 2-Pin RC Oscillator R versus Frequency (V Figure 12-12. 3-Pin RC Oscillator R versus Frequency (V MC68HC705K1 — Rev. 2.0 For More Information On This Product 1000 800 600 400 200 Electrical Specifications Go to: www.freescale.com Electrical Specifications Typical Oscillator Characteristics 5 5 Technical Data ...
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... Freescale Semiconductor, Inc. Electrical Specifications Figure 12-13. 2-Pin Oscillator R versus Frequency (V Figure 12-14. 3-Pin Oscillator R versus Frequency (V Technical Data 1000 800 600 400 200 Electrical Specifications For More Information On This Product, Go to: www.freescale.com 3 3 MC68HC705K1 — Rev. 2.0 ...
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... Freescale Semiconductor, Inc. Technical Data — MC68HC705K1 13.1 Contents 13.2 13.3 13.4 13.5 13.2 Introduction Package dimensions available at the time of this publication for the MC68HC705K1 are provided in this section. The packages are: • • • To make sure that you have the latest case outline specifications, contact one of the following: • ...
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... Freescale Semiconductor, Inc. Mechanical Specifications 13.3 Plastic Dual In-Line Package (Case 648) - 0.25 (0.010) 13.4 Small Outline Integrated Circuit (Case 751 16X M S 0.010 (0.25 14X Technical Data SEATING -T- PLANE 0.010 (0.25 -T- M SEATING K PLANE Mechanical Specifications For More Information On This Product, Go to: www ...
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... Freescale Semiconductor, Inc. 13.5 Ceramic Dual In-Line Package (Case 620 0.25 (0.010) MC68HC705K1 — Rev. 2.0 For More Information On This Product, Ceramic Dual In-Line Package (Case 620 16X 0.25 (0.010 SEATING T PLANE D 16X Mechanical Specifications Go to: www.freescale.com Mechanical Specifications NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14 ...
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... Freescale Semiconductor, Inc. Mechanical Specifications Technical Data Mechanical Specifications For More Information On This Product, Go to: www.freescale.com MC68HC705K1 — Rev. 2.0 ...
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... For More Information On This Product, Section 13. Ordering Information Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 MCU Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 lists the MC order numbers. Temperature Range + + +70 C – +85 C – +85 C – +85 C Ordering Information Go to: www.freescale.com Order Number (1) MC68HC705K1P (2) MC68HC705K1DW (3) MC68HC705K1S (4) MC68HC705K1CP MC68HC705K1CDW MC68HC705K1CS Technical Data ...
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... Freescale Semiconductor, Inc. Ordering Information Technical Data Ordering Information For More Information On This Product, Go to: www.freescale.com MC68HC705K1 — Rev. 2.0 ...
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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Home Page: www.freescale.com email: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 (800) 521-6274 480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center ...