N80C196KR Intel Corporation, N80C196KR Datasheet



Manufacturer Part Number
Intel Corporation

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5 530
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5 510
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The 83C196LC, 83C196LD are low-cost, pin-compatible replacements for the existing 87C196JT and
87C196JR, respectively. These products feature an enhanced synchronous serial I/O (SSIO) port for more
flexible communication to other devices. The enhanced SSIO is compatible with Motorola’s Serial Peripheral
Interface (SPI) protocol and National’s Microwire protocol. To optimize die size, the A/D converter was
removed for use in those applications that use an off-chip A/D converter.
The 83C196LC, 83C196LD are composed of a high-speed core with the following peripherals: an
asynchronous/synchronous serial I/O port (8096 compatible) with a dedicated 16-bit baud-rate generator; an
additional synchronous serial I/O port with full duplex master/slave transceivers; a flexible timer/counter
structure with prescaler, cascading, and quadrature capabilities; six modularized, multiplexed high-speed I/O
for capture and compare (called event processor array) with 200 ns resolution and double buffered inputs;
and a sophisticated, prioritized interrupt structure with programmable peripheral transaction server (PTS).
The 83C196LC has the highest memory density of the 52-pin MCS 96 microcontroller family, with 32 Kbytes
of on-chip ROM, 1 Kbyte of on-chip register RAM, and 512 bytes of code RAM. The high memory integration
of the 83C196LC supports high functionality in a low pin-count package and the use of the C programming
12 MHz standard; 18 MHz and 22 MHz are speed
22 MHz operation
32 Kbytes of on-chip ROM (LC)
16 Kbytes of on-chip ROM (LD)
1 Kbyte of on-chip register RAM (LC)
384 bytes of on-chip register RAM (LD)
512 bytes of on-chip code RAM
(LC only)
Register-to-register architecture
Peripheral transaction server (PTS)
with high-speed, microcoded interrupt
service routines
Full-duplex serial I/O port with
dedicated baud-rate generator
Enhanced full-duplex, synchronous
serial I/O port (SSIO)
This document contains information on products in the sampling and initial production
phases of development. The specifications are subject to change without notice. Verify
with your local Intel sales office that you have the latest datasheet before finalizing a
96 microcontroller family members are all high-performance microcontrollers with 16-bit CPUs.
83C196LC, 83C196LD
December 1996
High-speed event processor array
— Six capture/compare channels
— Two compare-only channels
— Two 16-bit software timers
Programmable 8- or 16-bit external bus
Design enhancements for EMI
Oscillator failure detection circuitry
SFR register that indicates the source
of the last reset
Watchdog timer (WDT)
Cost reduced replacements for the
87C196JT and 87C196JR.
–40° C to +125° C ambient temperature
52-pin PLCC package
Order Number: 272805-001

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N80C196KR Summary of contents

Page 1

... ROM, 1 Kbyte of on-chip register RAM, and 512 bytes of code RAM. The high memory integration of the 83C196LC supports high functionality in a low pin-count package and the use of the C programming language. COPYRIGHT © INTEL CORPORATION, 1996 ADVANCE INFORMATION Automotive High-speed event processor array — ...

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AUTOMOTIVE Watchdog Timer Peripheral Addr Bus (10) Peripheral Data Bus (16) Bus Control Bus Controller AD15:0 Bus-Control Interface Unit Queue Microcode Engine Source (16) Register RAM Memory 1 Kbyte (LC) Interface ALU 384 Bytes (LD) Unit Destination ...

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NOMENCLATURE OVERVIEW X XX Figure 2. Product Nomenclature Table 1. Description of Product Nomenclature Parameter Temperature and Burn-in Options Packaging Options Program-memory Options Process Information Product Family Device Speed ADVANCE INFORMATION AUTOMOTIVE — 83C196LC, 83C196LD XXXXX ...

Page 4

AUTOMOTIVE 2.0 PINOUT AD14 / P4.6 AD13 / P4.5 AD12 / P4.4 AD11 / P4.3 AD10 / P4.2 AD9 / P4.1 AD8 / P4.0 AD7 / P3.7 AD6 / P3.6 AD5 / P3.5 AD4 / P3.4 AD3 ...

Page 5

Table 3. Pin Assignment Arranged by Functional Categories Addr & Data Input/Output Name Pin Name AD0 22 P1.0/EPA0/T2CLK AD1 21 P1.1/EPA1 AD2 20 P1.2/EPA2/T2DIR AD3 19 P1.3/EPA3 AD4 18 P2.0/TXD AD5 17 P2.1/RXD AD6 16 P2.2 AD7 15 P2.4 AD8 ...

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AUTOMOTIVE 3.0 SIGNALS Name Type AD15:0 I/O Address/Data Lines These pins provide a multiplexed address and data bus. During the address phase of the bus cycle, address bits 0–15 are presented on the bus and can be ...

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Table 4. Signal Descriptions (Continued) Name Type EXTINT I External Interrupt In normal operating mode, a rising edge on EXTINT sets the EXTINT interrupt pending bit. EXTINT is sampled during phase 2 (CLKOUT high). The minimum high time is one ...

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AUTOMOTIVE Table 4. Signal Descriptions (Continued) Name Type P4.7:0 I/0 Port 4 This is a memory-mapped, 8-bit, bidirectional port with open-drain or complementary output modes. The pins are shared with the multiplexed address/data bus, which has complementary ...

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Table 4. Signal Descriptions (Continued) Name Type T2DIR I Timer 2 External Direction External direction (up/down) for timer 2. Timer 2 increments when T2DIR is high and decrements when it is low also used in conjunction with T2CLK ...

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AUTOMOTIVE Table 4. Signal Descriptions (Continued) Name Type XTAL1 I Input Crystal/Resonator or External Clock Input Input to the on-chip oscillator and the internal clock generators. The internal clock generators provide the peripheral clocks, CPU clock, and ...

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ADDRESS MAP Hex Address Range LC LD FFFF FFFF External device (memory or I/O) connected to A000 6000 address/data bus 9FFF 5FFF Program memory (internal nonvolatile or external memory); 2080 2080 see Note 1 207F 207F Special-purpose memory (internal ...

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AUTOMOTIVE 5.1 DC Characteristics Table 6. DC Characteristics at V Symbol Parameter I V supply current 40° +125° C – ambient) I Active mode supply cur rent (typical) I Idle ...

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Table 6. DC Characteristics at V Symbol Parameter C Pin capacitance S (any pin Weak pullup resistance WPU (approximate) NOTES: 1. All bidirectional pins except CLKOUT. CLKOUT is not pulled weakly high in reset. Bidirectional ...

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AUTOMOTIVE 5.2 AC Characteristics Test Conditions: capacitive load on all pins = 100 pF, rise and fall times = 10 ns, F Symbol Parameter The 83C196LC, 83C196LD meets these specifications F Oscillator Frequency 1 XTAL T Oscillator ...

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Table 7. AC Characteristics (Continued) Symbol Parameter The external memory system must meet these specifications T Address Valid to Input Data Valid AVDV T RD# Low to Input Data Valid RLDV T CLKOUT Low to Input Data Valid CLDV T ...

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AUTOMOTIVE XTAL1 CLKOUT T CLLH ALE/ADV# T LHLL RD# T AVLL Address Out AD15:0 (read) T AVDV WR# AD15:0 Address Out (write) AD15:8 (8-bit data bus XTAL1 CLCL CHCL XHCH T LLCH ...

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AC Characteristics — Serial Port, Shift Register Mode Test Conditions –40° +125° Table 9. Serial Port Timing — Shift Register Mode Symbol Parameter T Serial port clock period XLXL T Serial port ...

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AUTOMOTIVE 5.4 AC Characteristics — Synchronous Serial Port Table 10. Synchronous Serial Port Timing Symbol Parameter T Synchronous Serial Port Clock period CLCL T Synchronous Serial Port Clock falling edge to CLCH rising edge T Setup time ...

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External Clock Drive Table 11. External Clock Drive Symbol Parameter 1/T Oscillator Frequency XLXL T Oscillator Period (T XLXL XTAL T High Time XHXX T Low Time XLXX T Rise Time XLXH T Fall Time XHXL T XHXX 0.7 ...

Page 20

AUTOMOTIVE 5.6 Test Output Waveforms 3.5 V 0.45 V Note: AC testing inputs are driven at 3.5 V for a logic “1” and 0.45 V for a logic “0”. Timing measurements are made at 2.0 V for ...

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THERMAL CHARACTERISTICS All thermal impedance data is approximate for static air conditions at 1 watt of power dissipation. Values will change depending on operating conditions and the application. The Intel Packaging Handbook (order number 240800) describes Intel’s thermal impedance ...

Page 22

AUTOMOTIVE • I/O port pins. The following port pins do not exist in the 83C196LC and LD: P0.0–P0.1, P1.4–P1.7, P2.3 and P2.5, P5.1 and P5.4–P5.7, P6.2 and P6.3. Software can still read and write the associated Px_REG, ...

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