AM79C90JC Advanced Micro Devices, AM79C90JC Datasheet

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AM79C90JC

Manufacturer Part Number
AM79C90JC
Description
CMOS local area network controller for Ethernet (C-LANCE)
Manufacturer
Advanced Micro Devices
Datasheet

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Am79C90
CMOS Local Area Network Controller for Ethernet
(C-LANCE)
DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
The Am79C90 CMOS Local Area Network Controller
for Ethernet (C-LANCE) is a 48-pin VLSI device de-
signed to greatly simplify interfacing a microcomputer or
minicomputer to an IEEE 802.3/Ethernet Local Area
Network. The C-LANCE, in conjunction with the
Am7992B Serial Interface Adapter (SIA), Am7996 or
Am79C98 and Am79C100 Transceiver, and closely
coupled local memory and microprocessor, is intended
BLOCK DIAGRAM
Publication# 17881
Issue Date: January 1998
Compatible with Ethernet and IEEE 802.3
10BASE-5 Type A, and 10BASE-2 Type B,
“Cheapernet,” 10BASE-T
Easily interfaced with 80x86, 680x0, Am29000 ,
Z8000
On-board DMA and buffer management, 64-byte
Receive, 48-byte Transmit FIFOs
24-bit-wide linear addressing (Bus Master Mode)
Network and packet error reporting
PRELIMINARY
BM1/BUSAKO
DAL15:0
microprocessors
A23:16
BM0/BYTE
ALE/AS
Rev: C Amendment/0
READY
RESET
HOLD
READ
DALO
HLDA
INTR
DALI
ADR
DAS
CS
C-LANCE/
Interface
Interface
Parallel
Control
CPU
Bus
Bus
This document contains information on a product under development at Advanced Micro Devices. The
information is intended to help you evaluate this product. AMD reserves the right to change or discontinue
work on this proposed product without notice.
Detection
Address
Station
Path Control
DMA/Data
to provide the user with a complete interface module for
an Ethernet network. The Am79C90 is designed using
a scalable CMOS technology and is compatible with a
variety of microprocessors. On-board DMA, advanced
buffer management, and extensive error reporting and
diagnostics facilitate design and improve system
performance.
Back-to-back packet reception with as little as
0.5 s interframe spacing
Diagnostic Routines
— Internal/external loopback
— CRC logic check
— Time domain reflectometer
Low power consumption for power-sensitive
applications
Completely software- and hardware-compatible with
AMD’s LANCE device (Am7990) (see Appendix A)
Retry
Logic
Microprogram
Serial I/O
Interface
Store
RX
RCLK
TX
TCLK
CLSN
TENA
RENA
17881C-1
1

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AM79C90JC Summary of contents

Page 1

... Path Control Station Retry Address Logic Detection This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Microprogram Store RX RCLK ...

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AMD RELATED AMD PRODUCTS Part No. Description Am7996 IEEE 802.3/Ethernet/Cheapernet Tap Transceiver Am79C100 Twisted-Pair Ethernet Transceiver Plus (TPEX+) Am79C900 Integrated Local Area Communications Controller Am79C940 Media Access Controller for Ethernet (MACE Am79C960 PCnet-ISA Single-Chip Ethernet Controller (for ISA bus) Am79C961 ...

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TYPICAL ETHERNET/CHEAPERNET NODE Ethernet Local Local CPU Memory Local Bus Cheapernet Local Local CPU Memory Local Bus Typical Ethernet 10BASE-T Node Local Local CPU Memory Local Bus Local Local CPU Memory Local Bus AUI—Attachment Unit Interface DTE—Data Terminal Equipment P ...

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ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (valid combination) is formed by a combination of the elements below. AM79C90 DEVICE NUMBER/DESCRIPTION Am79C90 CMOS Local Area Network Controller for Ethernet ...

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PIN DESCRIPTION A16–A23 High Order Address Bus (Output, Three-State) Additional address bits to access a 24-bit address. These lines are driven as a Bus Master only. ADR Register Address Port Select (Input) When the C-LANCE is a Slave, ADR indicates ...

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Mode Bits BSWP = 0 Signal Line and BCON = 1 BYTE = L and Word DAL00 = L BYTE = L and Illegal DAL00 = H BYTE = H and Upper Byte DAL00 = H BYTE = H and ...

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READ (Input/Output, Three-State) Indicates the type of operation to be performed in the current bus cycle. This signal is an output when the C-LANCE is a Bus Master. High — Data is taken off the DAL lines by the C-LANCE. ...

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AMD FUNCTIONAL DESCRIPTION The parallel interface of the CMOS Local Area Network Controller for Ethernet (C-LANCE) has been designed to be “friendly” or easy to interface to a variety of popular microprocessors. These microprocessors include the Am29000, 80x86, 680x0, Z8000 ...

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Address Data Bus Bus Figure 2. C-LANCE/CPU Interfacing Demultiplexed Bus During initialization, the CPU loads the starting address of the initialization block into two internal control regis- ters. The C-LANCE has four internal control and status registers (CSR0 ...

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AMD under “Logical Address Filter.” The second logical ad- dress is a broadcast address where all nodes on the net- work receive the packet. The last receive mode of operation is referred to as “promiscuous mode” in which a node ...

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Transmit Descriptor for 1st Data Buffer Transmit Descriptor for 2nd Data Buffer Transmit Descriptor for 3rd Data Buffer Transmit Descriptor for Nth Data Buffer Receive Descriptor for 1st Data ...

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AMD C-LANCE CSR Registers Pointer to Initialization Block Initialization Block Mode of Operation Physical Address Logical Address Filter Pointer to Receive Ring Number of Receive Entries (N) Pointer to Transmit Ring Number of Transmit Entries (M) Figure 2-2. C-LANCE Memory ...

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BYTE scheme is chosen, the BM1 pin can be used for performing the function BUSAKO. BCON is also used to program pins for different DMA modes daisy chain DMA scheme, 3 signals are used (BUSRQ, HLDA, BUSAKO). ...

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AMD DAL0–DAL15 DAS READ READY (Output from C-LANCE) HOLD CS ADR Note: 1. There are two types of delays which depend on which internal register is accessed. Type 1 refers to access of CSR0, CSR3 and RAP. Type 2 refers ...

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DAL0–DAL15 DAS READ READY (Output from C-LANCE) HOLD CS ADR Read Sequence (Master Mode) A read cycle is begun by placing a valid address on DAL00 – DAL15 and A16 – A23. The BYTE MASK sig- nals are asserted to ...

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AMD T0 0 100 TCLK HOLD HLDA A16–A23 BM0, BM1 ALE DAS READY DAL0–DAL15 (Read) DALO (Read) DALI (Read) READ (Read) Figure 5-1. Bus Master Read Timing (Single DMA Cycle ...

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T0 0 TCLK HOLD HLDA A16–A23 BM0, BM1 ALE DAS READY DAL0–DAL15 (Write) DALO (Write) DALI (Write) READ (Write) Figure 5-2. Bus Master Write Timing (Single DMA Cycle ...

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AMD Differences Between Ethernet Versions 1 and 2 a. Version 2 specifies that the collision detect of the transceiver must be activated during the inter- packet gap time. b. Version 2 specifies some network management functions, such as reporting the ...

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PROGRAMMING This section defines the Control and Status Registers and the memory data structures required to program the Am79C90 (C-LANCE). Programming the Am79C90 (C-LANCE) The Am79C90 (C-LANCE) is designed to operate in an environment that includes close coupling with local ...

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AMD Register Address Port (RAP) Bit Name Description 15:02 RES Reserved. Read as zeroes. Write as zeroes. 01:00 CSR(1:0) CSR address select. READ/WRITE. Selects the CSR to be accessed through the RDP. RAP is cleared by Bus RESET. CSR(1 :0) ...

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Bit Name Description 11 MERR MEMORY ERROR is set when the C-LANCE is the Bus Master and has not received READY within 25.6 s after asserting the address on the DAL lines. When a Memory Error is detected, the receiver ...

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AMD Bit Name Description 03 TDMD TRANSMIT DEMAND, when set, causes the C-LANCE to access the Transmit Descriptor Ring without waiting for the polltime interval to elapse. TDMD need not be set to transmit a packet; it merely hastens the ...

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Control and Status Register 3 (CSR3) CSR3 allows redefinition of the Bus Master interface. READ/WRITE: Accessible only when the STOP bit 0 of CSR is ONE and RAP = 11. is cleared by RESET CSR setting the ...

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AMD Bit Name Description 15 PROM PROMISCUOUS PROM = 1, all incoming packets are accepted. 14:08 RES RESERVED. Read as zeroes. Write as zeroes. 07 EMBA Enable Modified Back-off Algorithm. When set (EMBA=1), enables the modified backoff algorithm. EMBA is ...

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Bit Name Description In loopback mode, transmit data chaining is not possible. Receive data chaining is possible if receive buffers are 32 bytes long to allow time for lookahead. 01 DTX DISABLE THE causes the C-LANCE to not access the ...

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AMD The Broadcast address, which consists of all ones is a special multicast address. Packets addressed to the broadcast address must be received by all nodes. Since broadcast packets are usually more common than other multicast packets, the broadcast address ...

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Buffer Management Buffer Management is accomplished through message descriptors organized in ring structures in memory. Each message descriptor entry is four words long. There are two rings allocated for the device: a Receive ring and a Transmit ring. The device ...

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AMD Bit Name Description 12 OFLO OVERFLOW error indicates that the receiver has lost all or part of the in- coming packet due to an inability to store the packet in a memory buffer before the internal Receive FIFO overflowed. ...

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Bit Name Description 15 OWN This bit indicates that the descriptor entry is owned by the host (OWN = the C-LANCE (OWN = 1). The host sets the OWN bit after filling the buffer pointed to by ...

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AMD Transmit Message Descriptor 3 (TMD3 Bit Name Description 15 BUFF BUFFER ERROR is set by the C-LANCE during transmission when the C-LANCE does not find the ENP flag in the current buffer and does not own ...

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Ring with the BUFF and UFLO error bits set. If the C-LANCE owns the 2nd DTE, it will also read the buffer address and ...

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AMD 127 Output A Packet Figure 8-1. Data Chaining (Transmit) C-LANCE 1 2 CPU CPU (Note 127 127 Transmit ...

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BSWP=0: FIFO BYTE n gets DAL <07:00> –don’t care gets DAL <15:08> BSWP=1: FIFO BYTE n gets DAL <15:08> –don’t care gets DAL <07:00> TRANSMISSION – BYTE READ FROM ODD MEMORY ADDRESS BSWP=0: FIFO BYTE n gets DAL <15:08> –don’t ...

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AMD and the CRC gets sampled internally on every byte boundary. The framing error is reported to the user as follows: If the number of the dribbling bits bits and there is no CRC error, then ...

Page 35

Collision—Microcode Interaction The microprogram uses the time provided by COLLI- SION JAM, INTERPACKET DELAY, and the backoff interval to restore the address and byte counts internally and starts loading the Transmit FIFO in anticipation of retransmission important that ...

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AMD Serial Transmission Serial transmission consists of sending an unbroken bit stream from the TX output pin consisting of: Preamble/SFD: 56 alternating ONES and ZEROES terminating with the SFD byte (10101011). Data: The serialized bit stream from the Transmit FIFO ...

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ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . Supply Voltages ...

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AMD SWITCHING CHARACTERISTICS Parameter No. Symbol Parameter Description 1 t TCLK Period TCT 2 t TCLK LOW Time TCL 3 t TCLK HIGH Time TCH 4 t Rise Time of TCLK TCR 5 t Fall Time of TCLK TCF 6 ...

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SWITCHING CHARACTERISTICS (continued) Parameter No. Symbol Parameter Description 31 t Data Hold Time After the Rising Edge RDAH of DAS (Bus Master Read Data Setup Time to the Falling Edge DDAS of DAS (Bus Master Write ...

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AMD SWITCHING CHARACTERISTICS (continued) Parameter No. Symbol Parameter Description 55 t ADR Hold Time After the Rising Edge of SAH DAS (Bus Slave ADR Setup Time to the Falling Edge of SAS DAS (Bus Slave Delay ...

Page 41

100 pF A. Normal and Three-State Outputs 100 pF B. Open-Drain Outputs (INTR, HOLD/BUSRQ, READY) Am79C90 17881B- 1.5 V 17881B-38 AMD ...

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AMD KEY TO SWITCHING WAVEFORMS SWITCHING WAVEFORMS (Note 1) CLSN RCLK RX RENA WAVEFORM INPUTS OUTPUTS Must Be Will Be Steady Steady May Will Be Change Changing from ...

Page 43

SWITCHING WAVEFORMS TCLK 8 TX TENA 6 RENA *During transmit, RENA input must be asserted (HIGH) and remain active-HIGH before TENA goes inactive (LOW). If RENA is deasserted before TENA is deasserted, LCAR will be reported in TMD HOLD HLDA ...

Page 44

AMD SWITCHING WAVEFORMS DAL0–DAL15 DAS READ READY (Output from C-LANCE) 74 HOLD CS ADR Note: 1. There are two types of delays which depend on which internal register is accessed. Type 1 refers to access of CSR0 CSR3 and RAP. ...

Page 45

SWITCHING WAVEFORMS DAL0–DAL15 DAS Read READY (Output from C-LANCE) 74 HOLD CS ADR Write Data Bus Slave Write Timing Am79C90 AMD 38 63 ...

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AMD SWITCHING WAVEFORMS Am79C90 ...

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SWITCHING WAVEFORMS Am79C90 AMD 47 ...

Page 48

APPENDIX A Hash Filter Generation Programs for Logical Addressing 80x86 computer program example to generate the hash filter, for multicast addressing in the C-LANCE ...

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F2 04C1 002B 0B C3 SETH30: 50 002D 002F 0031 0033 0035 ...

Page 50

AMD 170 PRINT “ENTER ETHERNET ADDRESS AS 6 HEXADECIMAL NUMBERS SEPARATED ” 180 PRINT “BY BLANKS. EACH NUMBER REPRESENTS ONE BYTE. THE LEAST ” 190 PRINT “SIGNIFICANT BIT OF THE FIRST BYTE IS THE FIRST BIT TRANSMITTED.” 200 PRINT “” ...

Page 51

C(1) = C(1) XOR 1: C(2) = C(2) XOR 1: C(4) = C(4) XOR 1 650 C(5) = C(5) XOR 1: C(7) = C(7) XOR 1: C(8) = C(8) XOR 1 660 C(10) = C(10) XOR 1: C(11) = ...

Page 52

AMD { int k,i, byte; /* temporary array indices */ int hashcode; /* the object of this program */ char buf[80]; /* holds input characters */ for (i=0;i<8;i++) ladrf[ clear log. adr. filter */ printf (”Enter Ethernet ...

Page 53

CRC ...

Page 54

AMD Table A-1 “Mapping of Logical Address to Filter Mask” can be used to find a multicast address that maps into a particular address filter bit. For example, address maps into bit 15. Therefore, ...

Page 55

APPENDIX B Comparison Between C-LANCE (Am79C90) and LANCE (Am7990) Devices OVERVIEW The Am79C90 C-LANCE device is a pin-for-pin equiv- alent for the Am7990 LANCE device. Using an ad- vanced 0.8-micron CMOS process, the C-LANCE device consumes less power than the ...

Page 56

Table B-1. Comparison Summary of the C-LANCE and LANCE Devices Description 1 Process/Power 0.8-micron CS-21S CMOS process Consumption FIFOs Dual FIFOs: 48-byte TX, 64-byte RX 3 Transmit Lockout Due to Will not occur with dual FIFOs and ...

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Detailed Description of Enhancements 1. Process/Power Consumption By using an advanced 0.8-micron CMOS process, the I specification for the C-LANCE device is reduced maximum, compared to the 270 mA maximum I specification for the LANCE device. ...

Page 58

Backoff Algorithm A selectable Modified Backoff Algorithm is provided in the C-LANCE device that can improve throughput in busy networks. Bit 7 of the Mode register (EMBA bit) is used to enable the Modified Backoff Algorithm. This bit is ...

Page 59

MAU must generate the collision signal within 0 1.6 s after the end of the transmit packet, which is typically early enough for the LANCE de- vice to detect it, even with its non-compliant 2- s window. However, ...

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ALE Behavior The LANCE device may drive the ALE pin LOW at the end of each bus mastership period when ACON = 1 (ALE/AS active low—AS mode). When the bus master- ship period ends, the ALE pin is tri-stated; ...

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Elimination of Burn-In Option The burn-in option for the C-LANCE is no longer avail- able. Thus, the ordering part number Am79C90PCB is no longer valid (see page 4 of the C-LANCE data sheet). 18. RX Descriptor Zero Buffer Byte ...

Page 62

... Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Am186, Am386, Am486, Am29000, b IMR, eIMR, eIMR+, GigaPHY, HIMIB, ILACC, IMR, IMR+, IMR2, ISA-HUB, MACE, Magic Packet, PCnet, PCnet- FAST , PCnet- FAST +, PCnet-Mobile, QFEX, QFEXr, QuASI , QuEST, QuIET, TAXIchip, TPEX, and TPEX Plus are trademarks of Advanced Micro Devices, Inc ...

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