VSC8117QP Vitesse Semiconductor Corp., VSC8117QP Datasheet

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VSC8117QP

Manufacturer Part Number
VSC8117QP
Description
ATM/SONET/SDH 622/155 Mb/s transceiver Mux/Demux with integrated clock generation and clock recovery
Manufacturer
Vitesse Semiconductor Corp.
Datasheet

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VSC8117
G52221-0, Rev. 4.1
1/8/00
Data Sheet
Features
General Description
Unit (PLL) for the high speed clock as well as a clock and data recovery unit (CRU) with 8 bit serial-to-parallel
and parallel-to-serial data conversion. The PLL clock is used for serialization in the transmit direction (Mux).
The recovered clock is used for deserialization in the receive direction (Demux). The demultiplexer contains
SONET/SDH frame detection and recovery. The device provides facility loopback, equipment loopback, and
loop timing modes. The part is packaged in a 64-pin PQFP with integrated heat spreader for optimum thermal
performance and reduced cost. The VSC8117 provides an integrated solution for ATM physical layers and
SONET/SDH systems applications.
Functional Description
networks and the lower speed User Network Interface devices such as the PM5355 S/UNI-622. The VSC8117
converts 8 bit parallel data at 77.76Mb/s or 19.44Mb/s to a serial bit stream at 622.08Mb/s or 155.52Mb/s
respectively. The device also provides a Facility Loopback function which loops the received high speed data
and clock (optionally recovered on-chip) directly to the high speed transmit outputs. A Clock Multiplier Unit
(CMU) is integrated into the transmit circuit to generate the high speed clock for the serial output data stream
from input reference frequencies of 19.44 or 77.76 MHz. The CMU can be bypassed with the recovered clock in
loop timing mode thus synchronizing the entire part to a single clock. The block diagram on page 2 shows the
major functional blocks associated with the VSC8117.
stream to an 8 bit parallel output at 19.44Mb/s or 77.76Mb/s respectively. A Clock Recovery Unit (CRU) is inte-
grated into the receive circuit to recover the high speed clock from the received serial data stream. The receive
section provides an Equipment Loopback function which will loop the low speed transmit data and clock back
through the receive section to the 8 bit parallel data bus and clock outputs. The VSC8117 also provides the
option of selecting between either its internal CRU’s recovered clock and data signals or optics containing a
The VSC8117 is an ATM/SONET/SDH compatible transceiver integrating an on-chip Clock Multiplication
The VSC8117 is designed to provide a SONET/SDH compliant interface between the high speed optical
The receive section provides the serial-to-parallel conversion, converting the 155.52Mb/s or 622.08Mb/s bit
• Operates at Either STS-3/STM-1 (155.52Mb/s)
• Compatible with Industry ATM UNI Devices
• On Chip Clock Generation of the 155.52MHz
• On Chip Clock Recovery of the 155.52MHz or
• 8 Bit Parallel TTL Interface
• SONET/SDH Frame Recovery
• Loss of Signal (LOS) Input & LOS Detection
or STS-12/STM-4 (622.08Mb/s) Data Rates
or 622.08MHz High Speed Clock (Mux)
622.08MHz High Speed Clock (Demux)
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
VITESSE
VITESSE SEMICONDUCTOR CORPORATION
SEMICONDUCTOR CORPORATION
ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
• +3.3V/5V programmable PECL Serial Interface
• Provides Equipment, Facilities and Split Loop-
• Provides TTL and PECL reference clock inputs
• Meets Bellcore, ITU and ANSI Specifications for
• Low Power - 1.0 Watts Typical
• 64 PQFP Package
back Modes as well as Loop Timing Mode
Jitter Performance
Page 1

Related parts for VSC8117QP

VSC8117QP Summary of contents

Page 1

Data Sheet VSC8117 Features • Operates at Either STS-3/STM-1 (155.52Mb/s) or STS-12/STM-4 (622.08Mb/s) Data Rates • Compatible with Industry ATM UNI Devices • On Chip Clock Generation of the 155.52MHz or 622.08MHz High Speed Clock (Mux) • On Chip Clock ...

Page 2

ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery CRU clock and data signals. (In this mode the VSC8117 operates just like the VSC8111 and VSC8116). The receive section also contains a SONET/SDH frame detector circuit which ...

Page 3

Data Sheet VSC8117 Transmit Section Byte-wide data is presented to TXIN[7:0] and is clocked into the part on the rising edge of TXLSCKOUT. TXLSCKOUT also latches TXIN[7:0] into the part as shown in Figure 1. The data is then serialized ...

Page 4

ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Loss of Signal The VSC8117 features Loss of Signal (LOS) detection. Loss of Signal is declared if the incoming serial data stream has no transition continuously for more ...

Page 5

Data Sheet VSC8117 RXDATAIN CRU Recovered Clock RXCLKIN TXDATAOUT FACLOOP Equipment Loopback The Equipment Loopback function is controlled by the EQULOOP signal. When the EQULOOP signal is set high, the Equipment Loopback mode is activated and the high speed transmit ...

Page 6

ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Split Loopback Equipment and facility loopback modes can be enabled simultaneously. In this case, high-speed serial data received (RXDATAIN) is mux’d through to the high-speed serial output (TXDATAOUT). ...

Page 7

Data Sheet VSC8117 Good analog design practices should be applied to the board design for these external components. Tightly controlled analog ground and power planes should be provided for the PLL portion of the circuitry. The dedi- cated PLL power ...

Page 8

ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Clock Recovery The fully monolithic Clock Recovery Unit (CRU) consists of a Phase Detector, a Frequency Detector, a Loop Filter and a Voltage Controlled Oscillator (VCO). The phase ...

Page 9

Data Sheet VSC8117 AC Timing Characteristics Figure 8: Receive High Speed Data Input Timing Diagram RXCLKIN+ RXCLKIN- RXDATAIN+ RXDATAIN- Table 2: Receive High Speed Data Input Timing Table (STS-12 Operation) Parameter T Receive clock period RXCLK T Serial data setup ...

Page 10

ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Table 4: Transmit Data Input Timing Table (STS-12 Operation) Parameter T Transmit data output byte clock period CLKOUT T Transmit data setup time with respect to TXLSCKOUT INSU ...

Page 11

Data Sheet VSC8117 Table 7: Receive Data Output Timing Table (STS-3 Operation) Parameter T Receive clock period RXCLKIN T Receive data output byte clock period RXLSCKT Time data on RXOUT [7:0] and FP is valid before and T RXVALID after ...

Page 12

ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Table 11: Clock Multiplier Unit Performance Name RCd Reference clock duty cycle RCj Reference clock jitter (RMS) @ 77.76 MHz ref RCj Reference clock jitter (RMS) @ 19.44 ...

Page 13

Data Sheet VSC8117 Table 13: PECL and TTL Inputs and Outputs Parameters Description Differential V Output Voltage OUT50 (PECL) Input HIGH V IH voltage (PECL) Input LOW V IL voltage (PECL) Differential Input V IN Voltage (PECL) I/P Common V ...

Page 14

ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Absolute Maximum Ratings Power Supply Voltage (V ) Potential to GND .................................................................................-0.5V to +4V DD PECL I/O Supply Voltage (V DDP DC Input Voltage (PECL inputs).......................................................................................... -0.5V to ...

Page 15

Data Sheet VSC8117 Package Pin Descriptions Table 15: Pin Identification Signal Pin RESET 1 LOOPTIM0 2 CMUFREQSEL 3 VDDP 4 TXDATAOUT+ 5 TXDATAOUT- 6 LOSDETEN_ 7 RXCLKIN+ 8 RXCLKIN- 9 VDDP 10 OOF 11 DSBLCRU 12 RXDATAIN+ 13 RXDATAIN- 14 ...

Page 16

ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Table 15: Pin Identification Signal Pin LOSPECL 33 VDD 34 VSS 35 REFCLK 36 VSSA 37 VDDA 38 CP1 39 CN1 40 CN2 41 CP2 42 VDDA 43 ...

Page 17

Data Sheet VSC8117 Package Information 64 Pin PQFP Package Drawings TYP G52221-0, Rev. 4.1 1/8/00 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE ...

Page 18

ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Package Thermal Characteristics The VSC8117 is packaged into a thermally-enhanced plastic quad flatpack (PQFP). This package adheres to the industry-standard EIAJ footprint for a 10x10mm body but has ...

Page 19

... Commercial Temperature ambient case VSC8117QP1 622Mb/s Mux/Dmux with CMU and CRU in 64 Pin PQFP Extended Temperature ambient to 115 C case VSC8117QP2 622Mb/s Mux/Dmux with CMU and CRU in 64 Pin PQFP Industrial Temperature, -40 C ambient case Notice Vitesse Semiconductor Corporation reserves the right to make changes in its products specifications or other information at any time without prior notice ...

Page 20

ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Application Notes DC Coupling and Terminating High-speed PECL I/Os The high speed signals on the VSC8117 (RXDATAIN, RXCLKIN, TXDATAOUT, REFCLKP, LOSPECL) use 3.3/5V programmable PECL I/Os which can ...

Page 21

Data Sheet VSC8117 Ground Planes The ground plane for the components used in the High Speed interface should be continuous and not sec- tioned in an attempt to provide isolation to various components. Sectioning of the ground planes tends to ...

Page 22

ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery V +3 INPUT R R GND REFCLK and TTL Inputs Page 22 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION ...

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