AL104 Allayer Communications, AL104 Datasheet - Page 66

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AL104

Manufacturer Part Number
AL104
Description
Manufacturer
Allayer Communications
Datasheet

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AL104 Revision 1.0
Rev. History (Prelim. 1.2 to 1.3)
1. Table 3: M2RXD1 changed to pin 52 and M2RXD0 changed to pin 51.
2. Table 13: SYSCLK is a 80MHz system clock.
3. Table 15: Register numbers have been changed.
4. Table 16: Register numbers have been changed.
5. Table 20: Section and table headings have been changed.
6. Table 21: Bits 8 and 9 have been added.
7. Table 23: Bit 13 has been added.
8. Table 32: Bit 14 has been added.
Rev. History (Prelim. 1.3 to 1.3a)
1. Changes were for layout of the Table of Contents.
2. Added memory information to appendix III.
3. Added new PHY management timing diagrams.
4. Added new RMII and MII timing diagrams.
Rev. History Prelim. 1.3a to Prelim. 1.4
1. Cleaned up SGRAM write and read tables.
2. Corrected queue management information.
Rev. History (Prelim. 1.4 to Rev. 1.0)
1. Fully released document.
9/00
Reference Only / Allayer Communications
66

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