VSC7125QN Vitesse Semiconductor Corp., VSC7125QN Datasheet

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VSC7125QN

Manufacturer Part Number
VSC7125QN
Description
1.0625Gb/s fibre channel transceiver. 3.3V supply
Manufacturer
Vitesse Semiconductor Corp.
Datasheet

Specifications of VSC7125QN

Case
QFP
Dc
00+

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Part Number:
VSC7125QN
Manufacturer:
MOT
Quantity:
6 220
VSC7125
Data Sheet
4/23/98
G52121-0, Rev. 4.1
Features
General Description
strained applications. It accepts 10-bit 8B/10B encoded transmit data, latches it on the rising edge of REFCLK
and serializes it onto the TX PECL differential outputs at a baud rate which is ten times the REFCLK frequency.
The VSC7125 also samples serial receive data on the RX PECL differential inputs, recovers the clock and data,
deserializes it onto the 10-bit receive data bus, outputs two recovered clocks at one twentieth of the incoming
baud rate and detects Fibre Channel “Comma” characters. The VSC7125 contains on-chip PLL circuitry for
synthesis of the baud-rate transmit clock, and extraction of the clock from the received serial stream. These cir-
cuits are fully monolithic and require no external components.
VSC7125 Block Diagram
COM_DET
EN_CDET
The VSC7125 is a full-speed Fibre Channel Transceiver optimized for Disk Drive and other space con-
REFCLK
• ANSI X3T11 Fibre Channel Compatible
• 10 Bit TTL Interface for Transmit and
• Monolithic Clock Synthesis and Clock
EWRAP
RCLKN
RCLK
1.0625 Gbps Full-duplex Transceiver
Receive Data
Recovery - No External Components
R0:9
T0:9
10
10
Resync
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Q D
Frame
Logic
D Q
VITESSE
VITESSE SEMICONDUCTOR CORPORATION
SEMICONDUCTOR CORPORATION
PLL Clock
Multiply
to Serial
Comma
Parallel
Serial to
Detect
Parallel
10
20
Retimed
Recovered
Data
Clock
Q D
• 106.25 MHz TTL Reference Clock
• Low Power Operation - 650 mW
• Suitable for Both Coaxial and Optical
• 64 Pin, 10mm or 14mm PQFP
• Single +3.3V Power Supply
Link Applications
Synthesized
Serial Data
Clock
Recovery
Clock
D Q
2:1
1.0625 Gbits/sec Fibre
Channel Transceiver
TX+
TX-
RX+
RX-
Page 1

Related parts for VSC7125QN

VSC7125QN Summary of contents

Page 1

Data Sheet VSC7125 Features • ANSI X3T11 Fibre Channel Compatible 1.0625 Gbps Full-duplex Transceiver • 10 Bit TTL Interface for Transmit and Receive Data • Monolithic Clock Synthesis and Clock Recovery - No External Components General Description The VSC7125 is ...

Page 2

Gbits/sec Fibre Channel Transceiver Functional Description Clock Synthesizer The VSC7125 clock synthesizer multiplies the reference frequency provided on the REFCLK pin achieve a baud rate clock at nominally 1.0625 GHz. The clock synthesizer contains a fully ...

Page 3

Data Sheet VSC7125 resulting parallel data will be captured by the adjoining protocol logic on the rising edges of RCLK and RCLKN. In order to maximize the setup and hold times available at this interface, the parallel data is loaded ...

Page 4

Gbits/sec Fibre Channel Transceiver Figure 2: Detection of a Properly Aligned Comma Character RCLK RCLKN COM_DET R0:9 TChar: 10 bit Transmission Character Figure 3: Detection and Resynchronization of an Improperly Aligned Comma Receiving Two Consecutive K28.5+TChar Transmission Words RCLK ...

Page 5

Data Sheet VSC7125 REFCLK T0:9 Data Valid 10 Bit Data AC Characteristics Table 1: Transmit AC Characteristics Parameters Description T0:9 Setup time to the rising T 1 edge of REFCLK T0:9 hold time after the T 2 rising edge of ...

Page 6

Gbits/sec Fibre Channel Transceiver Table 2: Receive AC Characteristics Parameters Description Data or COM_DET Valid T prior to RCLK/RCLKN 1 rise Data or COM_DET Valid T after RCLK or RCLKN 2 rise Deviation of RCLK rising edge to RCLKN ...

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Data Sheet VSC7125 RCLK RCLKN R0:9 Data Valid REFCLK Table 3: Reference Clock Requirements Parameters Description FR Frequency Range FO Frequency Offset DC REFCLK duty cycle T ,T REFCLK rise and fall time RCR RCF REFCLK Jitter Power REFCLK 5 ...

Page 8

Gbits/sec Fibre Channel Transceiver Figure 7: Parametric Measurement Information Serial Input Rise and Fall Time T r Receiver Input Eye Diagram Jitter Tolerance Mask Serial Output Load Page 8 741 Calle Plano, Camarillo, CA 93012 ...

Page 9

Data Sheet VSC7125 Figure 8: Transmitter Jitter Measurement Method BERT Pattern Generator 1.0625 GHz Clock RJ -K28.7 -K28.7 0011111000 0011111000 -K28.5 +K28.5 DJ 0011111010 1100000101 Random jitter (RJ) measurements performed according to Fibre Channel 4.3 Annex A, Test Methods, Section ...

Page 10

Gbits/sec Fibre Channel Transceiver DC Characteristics Parameters Description V Output HIGH voltage (TTL Output LOW voltage (TTL Output differential peak OUT75 to-peak voltage swing TX Output differential peak OUT50 to-peak voltage ...

Page 11

Data Sheet VSC7125 Package Pin Descriptions V SSD DDD DDD SSD V SSD N/C (Top View) Table 4: Pin Identification Pin # Name INPUTS - TTL 2-4, ...

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Gbits/sec Fibre Channel Transceiver Table 4: Pin Identification Pin # Name INPUT - TTL LOW for Normal Operation. When HIGH, an internal loopback path from the 19 EWRAP transmitter to the receiver is enabled and the TX outputs are ...

Page 13

Data Sheet VSC7125 Package Information 0.30 RAD. TYP. 0.20 RAD G52121-0, Rev. 4.1 4/23/98 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION 64-pin PQFP Package ...

Page 14

Gbits/sec Fibre Channel Transceiver Package Thermal Considerations The VSC7125 is packaged in either PQFP PQFP with internal heat spreaders. These packages use industry-standard EIAJ footprints, but have been enhanced to improve thermal ...

Page 15

Data Sheet VSC7125 Ordering Information The part number for this product is formed by a combination of the device number and the package style: Device Type: VSC7125: 1.0625 Gbps Transceiver Package Style (64-pin) QN: 14x14mm PQFP QU: 10x10mm PQFP Marking ...

Page 16

Gbits/sec Fibre Channel Transceiver Page 16 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC7125 G52121-0, Rev. 4.1 4/23/98 ...

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