S5933 AMCC (Applied Micro Circuits Corp), S5933 Datasheet

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S5933

Manufacturer Part Number
S5933
Description
Manufacturer
AMCC (Applied Micro Circuits Corp)
Datasheet

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D
The PCI Local bus concept was developed to break the PC data I/O bottleneck and clearly opens the door to increasing
system speed and expansion capabilities. The PCI Local bus moves high speed peripherals from the I/O bus and places
them closer to the system’s processor bus, providing faster data transfer between the processor and peripherals. The PCI
Local bus also addresses the industry’s need for a standard that is not directly dependent on the speed, size and type of
processor bus. It represents the first microprocessor independent bus offering performance more than adequate for the
most demanding applications, such as full-motion video.
Applied Micro Circuits Corporation (AMCC), the premier supplier of single chip solutions, has developed and pro-
duced the S5933 to solve the problem of interfacing applications to the PCI Local bus. The S5933, or ‘Matchmaker’, is
a powerful and flexible PCI controller supporting several levels of interface sophistication. At the lowest level, it can
serve simply as a PCI bus Target with modest transfer requirements. For high-performance applications, the S5933 can
become a Bus Master to attain the PCI Local bus peak transfer capability of 132 MBytes/sec.
The MatchMaker is an off-the-shelf, low-cost, standard product, which is PCI 2.1 compliant. And, since AMCC is a
member of the PCI Special Interest Group, the S5933 has been tested in "compliance workshops" along with other man-
ufacturer's PCI systems, chip sets and BIOSs. This removes the burden of compliance testing from the designer and thus
significantly reduces development time. Utilizing the S5933 allows the designer to focus on the actual application, not
debugging the PCI interface.
The MatchMaker allows special direct data accessing between the PCI bus and the user application through implemen-
tation of four definable Pass-Thru data channels. Each data channel is implemented by defining a Host memory segment
size and 8/16/32-bit user bus width. The addition of two 32 byte FIFOs, also used in S5933 Bus Mastering applications,
provides further versatility to data transfer capabilities. FIFO DMA transfers are supported using Address and Transfer
Count Registers. Four 32-bit Mailbox Registers coupled with a Status Register and extensive interrupt capabilities pro-
vide flexible user command or message transfers between the two buses. In addition, the S5933 also allows use of an
external serial, or byte-wide non-volatile memory to perform any pre-boot initialization requirements and to provide
custom expansion BIOS or POST code capability.
EATURES
ESCRIPTION
PCI 2.1 Compliant Master/Slave Device
Full 132 Mbytes/sec Transfer Rate
PCI Bus Operation DC to 33 Mhz
8/16/32 Bit Add-On User Bus
Four Definable Pass-Thru Regions
Two 32 Byte FIFOs
Sync/Async Add-On Bus Operation
Mail Box Registers w/Byte Level Status
Direct Mail Box Data Strobe/Interrupts
Big/Little Endian Conversions
Direct PCI & Add-On Interrupt Pins
Boot Loading from nvRAM or Byte Wide
Optional Expansion BIOS/POST Code
160 Pin PQFP
A
PPLICATIONS
6290 Sequence Drive, San Diego, California 92121-4358
High Speed Networking
Digital Video Applications
I/O Communications Ports
High Speed Data Input/Output
Multimedia Communications
Memory Interfaces
High Speed Data Acquisition
Data Encryption/Decryption
Intel i960 Interface
General Purpose PCI Interfacing
32-Bit PCI “MatchMaker”
February 12, 1997 Revised October 1998
800-755-2622 Fax: 619-450-9885
http://www.amcc.com
S5933

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S5933 Summary of contents

Page 1

... Applied Micro Circuits Corporation (AMCC), the premier supplier of single chip solutions, has developed and pro- duced the S5933 to solve the problem of interfacing applications to the PCI Local bus. The S5933, or ‘Matchmaker’ powerful and flexible PCI controller supporting several levels of interface sophistication. At the lowest level, it can serve simply as a PCI bus Target with modest transfer requirements ...

Page 2

... FIFO data channel under either Host or Add-On software control or Add-On hardware con- trol using dedicated S5933 signal pins. The S5933 signal pins are shown in Figure 2 right. The PCI Local Bus signals are detailed on the left side; Add-On Local Bus signal are detailed on the right side ...

Page 3

... Host processor from the PCI Local bus. These are the main registers through which the PCI Host configures S5933 operation and communicates with the Add-On Local bus. These registers encompass the PCI bus PCI Operation Registers ...

Page 4

... S5933 32-Bit PCI “MatchMaker” The optional nvRAM allows the Add-On card manufac- turer to initialize the S5933 with his specific Vendor ID and Device ID numbers along with desired S5933 opera- tion characteristics. The non-volatile memory feature also provides for the Expansion BIOS and POST code (power-on-self-test) options on the PCI bus ...

Page 5

... This is accomplished by either the Host CPU or Add-On logic. Data can be transferred between the two buses trans- parent to the PCI Host processor, however, the Add-On logic is required to service the S5933 Add-On Local bus. An indication of transfer completion can be seen by polling a status register done bit or S5933 signal pin or enabling a 'transfer count = 0' interrupt to either bus. ...

Page 6

... The PCI standard also provides the bandwidth required for many new, high-perfor- mance applications. The AMCC S5933 provides a flexible, low-cost, compliant interface to the PCI bus. The architecture of the S5933 makes it an excellent choice for cards being converted from the ISA/EISA standard, as well as newer applications requiring high data rates and bus mastering capabilities ...

Page 7

... RST# and INTA#. The maximum PCLK frequency for the S5933 is 33 MHz and the minimum Hz). RST# in Reset is used to bring all other signals within the S5933 to a known, consistent state. All PCI bus interface output signals are not driven (tri-stated), and open drain signals such as SERR# are floated. FRAME# s/t/s Frame ...

Page 8

... LOCK# in Lock. The lock signal provides for the exclusive use of a resource. The S5933 may be locked by one master at a time. The S5933 cannot lock a target when master. IDSEL in Initialization Device Select. This pin is used as a chip select during configuration read or write transactions ...

Page 9

... Address/Data Bus. The 32 bit Add-On data bus. The DQMODE signal configures the bus width for either bits. All DQ[31:0] signals have an internal pull-up. ADR[6:2} in Address [6:2]. These inputs select which S5933 register read from or written to used in conjunction with SELECT#, BE[3:0]# and WR# or RD#. The following table shows the register addresses. ADR [6 ...

Page 10

... Interrupt Request. This output signals Add-On logic a significant event has occurred as a result of activity within the S5933. FLT# in Float. Floats all S5933 output signals when asserted. This signal is connected to an inter- nal pull-up resistor. SNV in Serial Non-Volatile Device. This input, when high, indicates that a serial boot device or that no boot device in present ...

Page 11

... BPCLK WRFIFO# DQ[31:0] WRFULL FWE Notes: 1. The WRFULL is an example relative to data 2, if data 2 were to fill the FIFO. 32-Bit PCI “MatchMaker” New Valid Old Valid New Valid Old Valid 6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622 S5933 4 11 ...

Page 12

... S5933 32-Bit PCI “MatchMaker” Multiple Synchronous RD# Operation BPCLK SELECT# ADR[6:2] BE[3:0] 1 DQ[31:0] RD# RDEMPTY FRF Multiple Synchronous WR# Operation BPCLK SELECT# ADR[6:2] BE[3:0 DQ[31:0] WR# WRFULL FWE 6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622 ...

Page 13

... PCI “MatchMaker” C ONDITIONS Min Max Units Test Conditions 4.75 5.25 Volts To PCI Spec 2.2 2.0 - Volts -0.5 0.8 Volts 2.4 - Volts out - 0.55 Volts ma out - 2.7 VDC 0.5 VDC 6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622 S5933 Notes ...

Page 14

... S5933 32-Bit PCI “MatchMaker” PCI Local Bus Device Controls Power & Ground 6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622 14 56 AD0 55 AD1 54 AD2 52 AD3 48 AD4 47 S5933 MatchMaker AD5 46 AD6 44 AD7 42 AD8 40 AD9 39 AD10 38 AD11 36 AD12 35 AD13 34 AD14 32 AD15 14 AD16 ...

Page 15

... AD27 154 AD26 155 AD25 156 DQ16 157 AD24 158 C/BE3# 159 IDSEL 160 32-Bit PCI “MatchMaker” S5933 160 PQFP 6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622 S5933 DQ12 80 79 DQ13 DQ14 78 77 DQ24 DQ15 76 SELECT WR# EA3 73 72 ...

Page 16

... S5933 32-Bit PCI “MatchMaker” ACKAGE NFORMATION 160 PQFP Pin 1 Indicator 6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622 S5933 160 PQFP Radius Detail Symbol MIN NOM MAX 4. 31.90 BSC D1 28.00 BSC E 31.90 BSC E1 28.00 BSC L 0.65 0.80 1.03 e 0.65 BSC B 0 ...

Page 17

... AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYS- TEMS OR OTHER CRITICAL APPLICATIONS. Copyright © 1998 Applied Micro Circuits Corporation 6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622 S5933 32-Bit PCI “MatchMaker” 17 ...

Page 18

Sales And Representative Offices PPLIED ICRO IRCUITS United States Regional Sales Managers Southwest Mike Vogel Northwest Sam Laymoun Mid-US George Amundson Northeast Dave Crary Southeast Joey Carabetta Factory Application Engineers Northwest Issa Shokeh Mid-US Wes Stalcup Northeast ...

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