MC68HCP11A1FN Motorola, MC68HCP11A1FN Datasheet

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MC68HCP11A1FN

Manufacturer Part Number
MC68HCP11A1FN
Description
MC68HCP11A1FN8-Bit Microcontrollers
Manufacturer
Motorola
Datasheet

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Technical Summary
8-Bit Microcontrollers
1 Introduction
1.1 Features
© MOTOROLA INC., 1991, 1996
MOTOROLA
SEMICONDUCTOR
TECHNICAL DATA
This document contains information on a new product. Specifications and information herein are subject to change without notice.
The MC68HC11A8, MC68HC11A1, and MC68HC11A0 high-performance microcontroller units (MCUs)
are based on the M68HC11 Family. These high speed, low power consumption chips have multiplexed
buses and a fully static design. The chips can operate at frequencies from 3 MHz to dc. The three MCUs
are created from the same masks; the only differences are the value stored in the CONFIG register, and
whether or not the ROM or EEPROM is tested and guaranteed.
For detailed information about specific characteristics of these MCUs, refer to the M68HC11 Reference
Manual (M68HC11RM/AD).
• M68HC11 CPU
• Power Saving STOP and WAIT Modes
• 8 Kbytes ROM
• 512 Bytes of On-Chip EEPROM
• 256 Bytes of On-Chip RAM (All Saved During Standby)
• 16-Bit Timer System
• 8-Bit Pulse Accumulator
• Real-Time Interrupt Circuit
• Computer Operating Properly (COP) Watchdog System
• Synchronous Serial Peripheral Interface (SPI)
• Asynchronous Nonreturn to Zero (NRZ) Serial Communications Interface (SCI)
• 8-Channel, 8-Bit Analog-to-Digital (A/D) Converter
• 38 General-Purpose Input/Output (I/O) Pins
• Available in 48-Pin Dual In-Line Package (DIP) or 52-Pin Plastic Leaded Chip Carrier (PLCC)
— 3 Input Capture Channels
— 5 Output Compare Channels
— 15 Bidirectional I/O Pins
— 11 Input-Only Pins and 12 Output-Only Pins (Eight Output-Only Pins in 48-Pin Package)
MC68HC11A8
MC68HC11A1
MC68HC11A0
by MC68HC11A8TS/D
Order this document

MC68HCP11A1FN Summary of contents

Page 1

... Input-Only Pins and 12 Output-Only Pins (Eight Output-Only Pins in 48-Pin Package) • Available in 48-Pin Dual In-Line Package (DIP) or 52-Pin Plastic Leaded Chip Carrier (PLCC) This document contains information on a new product. Specifications and information herein are subject to change without notice. © MOTOROLA INC., 1991, 1996 Order this document by MC68HC11A8TS/D ...

Page 2

... No ROM, No EEPROM Comments Family built around this device ROM disabled ROM and EEPROM disabled MC Order Number MC68HC11A8P1 No ROM MC68HC11A1P No ROM MC68HC11A1VP No ROM MC68HC11A1MP MC68HCP11A1P MC68HCP11A1VP MC68HCP11A1MP MC68HC11A0P MC68HC11A8FN1 No ROM MC68HC11A1FN No ROM MC68HC11A1VFN No ROM MC68HC11A1MFN MC68HCP11A1FN MC68HCP11A1VFN MC68HCP11A1MFN MC68HC11A0FN MC68HC11A8 MC68HC11A8TS/D ...

Page 3

... Memory Maps ..................................................................................................................................7 3 Resets and Interrupts .............................................................................................................................13 4 Electrically Erasable Programmable Read-Only Memory (EEPROM) ...................................................17 5 Parallel Input/Output...............................................................................................................................19 6 Serial Communications Interface (SCI) ..................................................................................................23 7 Serial Peripheral Interface (SPI)............................................................................................................. 29 8 Main Timer..............................................................................................................................................32 9 Pulse Accumulator..................................................................................................................................38 10 Analog-to-Digital Converter .................................................................................................................. 41 MC68HC11A8 MC68HC11A8TS/D TABLE OF CONTENTS Page MOTOROLA 3 ...

Page 4

... PB0 A7/D7 PC7 A6/D6 PC6 A5/D5 PC5 A4/D4 PC4 A3/D3 PC3 A2/D2 PC2 A1/D1 PC1 A0/D0 PC0 R/W STRB AS STRA PARALLEL I/O EQUIVALENT TO MC68HC24 Figure 1 MC68HC11A8 Block Diagram MOTOROLA 4 COP OSCILLATOR TIMER SYSTEM PERIODIC INTERRUPT CPU 256 512 BYTES BYTES RAM EEPROM 8 KBYTES ROM V DD POWER V SS IRQ INTERRUPT XIRQ LOGIC ...

Page 5

... XTAL 8 PC0/A0/D0 9 PC1/A1/D1 10 PC2/A2/D2 11 PC3/A3/D3 12 PC4/A4/D4 13 PC5/A5/D5 14 PC6/A6/D6 15 PC7/A7/D7 16 RESET 17 XIRQ 18 IRQ 19 PD0/RxD 20 Figure 2 52-Pin PLCC Pin Assignments MC68HC11A8 MC68HC11A8TS/D 46 PE5/AN5 1 45 PE1/AN1 44 PE4/AN4 43 PE0/AN0 42 PB0/A8 41 PB1/A9 40 PB2/A10 39 PB3/A11 38 PB4/A12 37 PB5/A13 36 PB6/A14 35 PB7/A15 34 PA0/IC3 MOTOROLA 5 ...

Page 6

... The expansion bus is made up of ports B and C and control signals AS and R/W. The address, R/W, and AS signals are active and valid for all bus cycles including accesses to internal mem- ory locations. The following figure illustrates a recommended method of demultiplexing low-order ad- dresses from data at port C. MOTOROLA ...

Page 7

... In special test and special bootstrap modes, reset and interrupt vectors are located at $BFC0 through $BFFF. MC68HC11A8 MC68HC11A8TS/D A15 A14 A13 A12 A11 A10 A9 A8 MC54/74HC373 MOTOROLA 7 ...

Page 8

... EXT $1000 EXT $B600 EXT $E000 $FFFF SINGLE EXPANDED CHIP MUX BOOTSTRAP MOTOROLA 8 EXT EXT EXT SPECIAL SPECIAL TEST Figure 5 Memory Map 0000 256 BYTES RAM (CAN BE REMAPPED TO ANY 4K PAGE BY THE INIT REGISTER) 00FF 1000 64 BYTE REGISTER BLOCK (CAN BE REMAPPED TO ANY ...

Page 9

... TOC2 (High) 1 Bit 0 TOC2 (Low) 9 Bit 8 TOC3 (High) 1 Bit 0 TOC3 (Low) 9 Bit 8 TOC4 (High) 1 Bit 0 TOC4 (Low) 9 Bit 8 TOC5 (High) 1 Bit 0 TOC5 (Low) OM5 OL5 TCTL1 EDG3B EDG3A TCTL2 IC2I IC3I TMSK1 IC2F IC3F TFLG1 PR1 PR0 TMSK2 0 0 TFLG2 MOTOROLA 9 ...

Page 10

... ADPU CSEL IRQE $103A Bit 7 6 $103B ODD EVEN $103C RBOOT SMOD $103D RAM3 RAM2 RAM1 $103E TILOP 0 OCCR $103F 0 0 MOTOROLA PEDGE MSTR CPOL CPHA 0 MODF SCP0 RCKB SCR2 0 M WAKE RIE ...

Page 11

... IRV PSEL3 PSEL2 PSEL1 — Mode Single Chip Expanded Multiplexed Special Bootstrap Special Test RAM0 REG3 REG2 REG1 $103C 1 Bit 0 PSEL0 0 1 Latched at Reset RBOOT SMOD MDA $103D 1 Bit 0 REG0 0 1 MOTOROLA 11 ...

Page 12

... ROMON — ROM Enable In single-chip mode, ROMON is forced to one out of reset ROM removed from the memory map ROM present in the memory map EEON — EEPROM Enable 0 = EEPROM is removed from the memory map 1 = EEPROM is present in the memory map MOTOROLA CBYP ...

Page 13

... There are four RTI signal rates available in the MC68HC11A8. The MCU oscillator frequency and the value of two software-accessible control bits, RTR1 and RTR0, in the pulse accumulator control register (PACTL) determine these signal rates. Refer to 8 Main Timer for more information about PACTL. MC68HC11A8 MC68HC11A8TS/D MOTOROLA 13 ...

Page 14

... Refer to 10 Analog-to-Digital Converter . CSEL —Clock Select Refer to 10 Analog-to-Digital Converter . IRQE — IRQ Select Edge-Sensitive Only 0 = Low logic level recognition 1 = Falling edge recognition MOTOROLA 14 Interrupt Source SCI Transmit Complete SCI Transmit Data Register Empty SCI Idle Line Detect ...

Page 15

... MHz 2.0 MHz IRV PSEL3 PSEL2 PSEL1 — XTAL = 12.0 MHz Timeout –0/+10.9 ms 10.923 ms 43.691 ms 174.76 ms 699.05 ms 3.0 MHz $103A 1 Bit $103C 1 Bit 0 PSEL0 0 1 MOTOROLA 15 ...

Page 16

... COP disabled (does not force reset on timeout) ROMON — ROM Enable Refer to 2 Operating Modes and Memory Maps . EEON — EEPROM Enable Refer to 2 Operating Modes and Memory Maps . MOTOROLA 16 Interrupt Source Promoted Timer Overflow Pulse Accumulator Overflow Pulse Accumulator Input Edge ...

Page 17

... All 512 bytes of EEPROM are erased 1 = Erase only one 16-byte row of EEPROM BYTE MC68HC11A8 MC68HC11A8TS BYTE ROW ERASE EELAT ROW Action 0 Bulk Erase (All 512 Bytes) 1 Row Erase (16 Bytes) 0 Byte Erase 1 Byte Erase $103B Bit 0 EEPGM 0 MOTOROLA 17 ...

Page 18

... NOCOP — COP system disable Refer to 3 Resets and Interrupts. ROMON — ROM Enable Refer to 2 Operating Modes and Memory Maps. EEON — EEPROM Enable 0 = EEPROM is removed from the memory map 1 = EEPROM is present in the memory map MOTOROLA NOSEC ...

Page 19

... STRB. The external system responds by activating the STRA input, which forces the MCU to drive the data in PORTCL out on all of the port C lines. This mode variation does not allow part of port used for static inputs while other port C pins are being used for handshake outputs. Refer to the PIOC register description. MC68HC11A8 MC68HC11A8TS/D MOTOROLA 19 ...

Page 20

... Pulsed handshake (strobe B pulses high for two E-clock cycles) EGA — Active Edge for Strobe STRA falling edge selected 1 = STRA rising edge selected INVB — Invert Strobe Active level is logic zero 1 = Active level is logic one MOTOROLA PA4 ...

Page 21

... Normal out- puts if STRA at put port, active level, unaffected follows DDRC in hand- if STRA not at shake active level modes Follow DDRC $1003 1 Bit 0 PC1 PC0 PC1 PC0 0 0 ADDR0/ DATA0 $1004 1 Bit 0 PB1 PB0 PB1 PB0 0 0 ADDR8 $1005 1 Bit 0 PCL0 U U MOTOROLA 21 ...

Page 22

... PAEN — Pulse Accumulator System Enable Refer to 9 Pulse Accumulator. PAMOD — Pulse Accumulator Mode Refer to 9 Pulse Accumulator. PEDGE — Pulse Accumulator Edge Control Refer to 9 Pulse Accumulator. RTR1, RTR0 — Real-Time Interrupt Rate Refer to 8 Main Timer. MOTOROLA DDC4 DDC3 ...

Page 23

... REQUESTS REQUEST Figure 6 SCI Transmitter Block Diagram MC68HC11A8 MC68HC11A8TS/D (WRITE ONLY) 8 FORCE PIN DIRECTION (OUT) TRANSMITTER CONTROL LOGIC SCSR INTERRUPT STATUS TDRE TIE TC TCIE SCCR2 SCI CONTROL 2 DDD1 PIN BUFFER PD1 AND CONTROL TxD 8 8 INTERNAL DATA BUS 11 SCI TX BLOCK MOTOROLA 23 ...

Page 24

... RxD AND CONTROL DISABLE DRIVER RE M WAKEUP LOGIC SCCR1 SCI CONTROL 1 SCI Tx SCI INTERRUPT REQUESTS REQUEST Figure 7 SCI Receiver Block Diagram MOTOROLA SHIFT REGISTER DATA ( RECOVERY SCSR SCI STATUS 1 RDRF RIE IDLE ILIE OR RIE SCCR2 SCI CONTROL 2 ...

Page 25

... Highest Baud Rate (Prescaler Output from Previous Table) By 4800 9600 1 4800 9600 2 2400 4800 4 1200 2400 8 600 1200 16 300 600 32 150 300 64 — 150 128 — — $102B 1 Bit 0 SCR0 U U 12.0 MHz (Baud) 187.5K 62.5K 38.4K 46.88K 14.42K 38.4K 38.4K 19.2K 9600 4800 2400 1200 600 300 MOTOROLA 25 ...

Page 26

... If M bit is set, R8 stores ninth bit in receive data character. T8 — Transmit Data Bit bit is set, T8 stores ninth bit in transmit data character. M — Mode (Select Character Format Start bit, 8 data bits, 1 stop bit 1 = Start bit, 9 data bits, 1 stop bit MOTOROLA 26 INTERNAL BUS CLOCK (PH2 0:0 ...

Page 27

... TC — Transmit Complete Flag Set if transmitter is idle (no data, preamble, or break transmission in progress). Cleared by SCSR read with TC set followed by SCDR write. MC68HC11A8 MC68HC11A8TS ILIE TE RE RWU IDLE $102D Bit 0 SBK 0 $102E Bit MOTOROLA 27 ...

Page 28

... Set if a zero is detected where a stop bit was expected. Cleared by SCSR read with FE set followed by SCDR read. SCDR — SCI Data Register Bit R7/T7 R6/T6 R5/T5 RESET Receive and transmit are double buffered. Reads access the receive data buffer and writes access the transmit data buffer. MOTOROLA R4/T4 R3/T3 R2/T2 R1/ NOTE ...

Page 29

... INTERNAL DATA BUS Figure 9 SPI Block Diagram DDD4 DDD3 DDD2 DDD1 PD4/ PD3/ PD2/ PD1/ SCK MOSI MISO TxD MISO S PD2 M M MOSI PD3 S S SCK PD4 M SS PD5 11 SPI BLOCK $1009 Bit 0 DDD0 0 PD0/ RxD MOTOROLA 29 ...

Page 30

... SCK (CPOL = 0) SCK (CPOL = 1) SAMPLE INPUT MSB (CPHA = 0) DATA OUT SAMPLE INPUT (CPHA = 1) DATA OUT SS (TO SLAVE ASSERTED 2. MASTER WRITES TO SPDR 3. FIRST SCK EDGE 4. SPIF SET 5. SS NEGATED MOTOROLA MSTR CPOL CPHA ...

Page 31

... Bit SPI is double buffered in, single buffered out. MC68HC11A8 MC68HC11A8TS/D E-Clock Frequency at Divide MHz (Baud) 2 1.0 MHz 4 500 kHz 16 125 kHz 32 62.5 kHz MODF NOTE $1029 Bit $102A Bit 0 Bit 0 MOTOROLA 31 ...

Page 32

... RTR[1: 8.192 16.384 32.768 65.536 ms MOTOROLA 32 Table 6 Timer Summary XTAL Frequencies 8.0 MHz 12.0 MHz 2.0 MHz 3.0 MHz 500 ns 333 ns Main Timer Count Rates 500 ns 333 ns 32.768 ms 21.845 ms 2.0 s 1.333 s 131 ...

Page 33

... Figure 11 Main Timer 9 INTERRUPT REQUESTS (FURTHER QUALIFIED BY I BIT IN CCR) TO PULSE ACCUMULATOR PIN 8 FUNCTIONS PA7/OC1/ BIT 7 PAI 7 PA6/OC2/ BIT 6 OC1 6 PA5/OC3/ BIT 5 OC1 5 PA4/OC4/ BIT 4 OC1 4 PA3/OC5/ BIT 3 IC4/OC1 3 BIT 2 PA2/IC1 2 BIT 1 PA1/IC2 1 BIT 0 PA0/IC3 PORT A PIN CONTROL CAPTURE COMPARE BLOCK MOTOROLA 33 ...

Page 34

... TCNT resets to $0000. In normal modes, TCNT is read-only. TIC1–TIC3 — Timer Input Capture $1010 Bit 15 14 $1011 Bit 7 6 $1012 Bit 15 14 $1013 Bit 7 6 $1014 Bit 15 14 $1015 Bit 7 6 TICx not affected by reset. MOTOROLA FOC4 FOC5 OC1M4 OC1M3 0 0 ...

Page 35

... Capture on any edge $1016–$101F 9 Bit 8 High TOC1 1 Bit 0 Low 9 Bit 8 High TOC2 1 Bit 0 Low 9 Bit 8 High TOC3 1 Bit 0 Low 9 Bit 8 High TOC4 1 Bit 0 Low 9 Bit 8 High TOC5 1 Bit 0 Low $1020 1 Bit 0 OM5 OL5 0 0 $1021 1 Bit 0 EDG3B EDG3A 0 0 MOTOROLA 35 ...

Page 36

... Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in TMSK2 enable the corresponding interrupt sources. PR1 and PR0 — Timer Prescaler Select In normal modes, PR1 and PR0 can only be written once, and the write must be within 64 cycles after reset. Refer to Table 6 for specific timing values. MOTOROLA ...

Page 37

... PEDGE Table 8 Real-Time Interrupt Rates XTAL = 4.0 MHz XTAL = 8.0 MHz 8.19 ms 4.096 ms 16.38 ms 8.192 ms 32.77 ms 16.384 ms 65.54 ms 32.768 ms 1.0 MHz 2.0 MHz $1025 1 Bit $1026 1 Bit 0 RTR1 RTR0 0 0 XTAL = 12.0 MHz 2.731 ms 5.461 ms 10.923 ms 21.845 ms 3.0 MHz MOTOROLA 37 ...

Page 38

... INPUT BUFFER PAI/ AND OC1 EDGE DETECTOR OUTPUT BUFFER FROM MAIN TIMER OC1 FROM PACTL CONTROL DDRA7 Figure 12 Pulse Accumulator System Block Diagram MOTOROLA 38 Table 9 Pulse Accumulator Timing Common XTAL Frequencies 4.0 MHz (E) 1.0 MHz (1/E) 1000 ns 1 count — 64.0 s 16.384 ms PAI EDGE PAEN ...

Page 39

... DDRA7 — Data Direction for Port A Bit 7 Refer to 5 Parallel Input/Output. MC68HC11A8 MC68HC11A8TS PAII 0 0 PR1 NOTE PAIF PEDGE 0 0 RTR1 $1024 Bit 0 PR0 0 $1025 Bit $1026 Bit 0 RTR0 0 MOTOROLA 39 ...

Page 40

... PACNT — Pulse Accumulator Counter Bit Bit RESET Can be read and written. MOTOROLA 40 PEDGE Action on Clock 0 PAI falling edge increments the counter 1 PAI rising edge increments the counter 0 A zero on PAI inhibits counting 1 A one on PAI inhibits counting ...

Page 41

... Figure 13 A/D Converter Block Diagram MC68HC11A8 MC68HC11A8TS/D provide the reference supply voltage inputs. Refer to the A/D converter 8-BIT CAPACITIVE DAC WITH SAMPLE AND HOLD SUCCESSIVE APPROXIMATION REGISTER AND CONTROL ADCTL A/D CONTROL RESULT REGISTER INTERFACE ADR3 A/D RESULT INTERNAL DATA BUS ADR4 A/D RESULT 4 EA9 A/D BLOCK MOTOROLA 41 ...

Page 42

... Set after an A/D conversion cycle. Cleared when ADCTL is written. SCAN — Continuous Scan Control four conversions and stop 1 = Convert four channels in selected group continuously MULT — Multiple Channel/Single Channel Control 0 = Convert single channel selected 1 = Convert four channels in selected group MOTOROLA 42 MSB BIT 6 BIT 5 BIT 4 BIT 3 ...

Page 43

... Result in ADRx if MULT = 1 ADR1 ADR2 ADR3 ADR4 ADR1 ADR2 ADR3 ADR4 ADR1–ADR4 ADR1 ADR2 ADR3 ADR4 $1031–$1034 1 Bit 0 1 Bit 0 ADR1 1 Bit 0 ADR2 1 Bit 0 ADR3 1 Bit 0 ADR4 2 1 Bit 0 0.78% 0.39% 0.0391 0.0195 $1039 1 Bit 0 CR1* CR0 MOTOROLA 43 ...

Page 44

... Refer to 3 Resets and Interrupts. DLY — Enable Oscillator Start-Up Delay on Exit from STOP Refer to 3 Resets and Interrupts. CME — Clock Monitor Enable Refer to 3 Resets and Interrupts. CR1, CR0 — COP Timer Rate Select Refer to 3 Resets and Interrupts. MOTOROLA 44 MC68HC11A8 MC68HC11A8TS/D ...

Page 45

... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...

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