UPD30122F1-180-GA1 NEC, UPD30122F1-180-GA1 Datasheet
UPD30122F1-180-GA1
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UPD30122F1-180-GA1 Summary of contents
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... The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. U15585EJ3V0DS00 (3rd edition) ...
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ORDERING INFORMATION Part Number µ PD30122F1-150-GA1 224-pin plastic FBGA (16 × 16) µ PD30122F1-180-GA1 224-pin plastic FBGA (16 × 16) PIN CONFIGURATION • 224-pin plastic FBGA (16 × 16) µ PD30122F1-150-GA1 µ PD30122F1-180-GA1 Bottom view ...
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Pin No. Power Pin Name Pin No. Note Supply A1 3.3 V CLKOUT C14 A2 1 C15 C16 DD A4 3.3 V CLKX1 C17 A5 3.3 V CLKX2 C18 A6 3.3 ...
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Pin No. Power Pin Name Pin No. Note Supply P4 3.3 V GND3 T4 P15 3.3 V RTS#/CLKSEL1 T5 P16 3.3 V DCTS#/GPIO35 T6 P17 3.3 V TxD/CLKSEL2 T7 P18 3.3 V NWIREEN/HLDAK 3.3 V DATA21/GPIO21 T9 R2 ...
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Pin Identification AD(31:0): Address/data bus ADD(24:1): Address bus BATTINH: Battery inhibit BATTINT#: Battery interrupt request BKTGIO#: Break trigger I/O CAS: Column address strobe CBE(3:0): Command/byte enable CGND: GND for oscillator CKE(1:0): Clock enable CLKSEL(2:0): Clock select CLKOUT: Clock output CLKRUN: ...
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... INTERNAL BLOCK DIAGRAM AND EXAMPLE OF CONNECTION OF EXTERNAL BLOCKS 32.768 kHz 18.432 MHz TM V 4173 RC Touch panel PC card LCDC LCD panel SDRAM ROM/ Flash memory CPU CORE INTERNAL BLOCK DIAGRAM Virtual address bus Internal data bus Bus Control (o) interface Control (i) Address/data (o) Address/data (i) ...
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PIN FUNCTIONS ..................................................................................................................................8 1.1 Pin Functions ............................................................................................................................................. 8 1.2 Pin Status in Specific States .................................................................................................................. 17 1.3 Pin Handling and I/O Circuit Types........................................................................................................ 21 1.4 Pin I/O Circuits ......................................................................................................................................... 23 2. ELECTRICAL SPECIFICATIONS .......................................................................................................24 3. PACKAGE DRAWING........................................................................................................................56 4. RECOMMENDED ...
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... Bank 2 Bank 1 Bank 0 DQM3 Output The function differs depending on the setting of the DBUS32 pin and the connected device. • When DBUS32 = 1 and SDRAM is accessed: This is the byte enable signal for DATA(31:24) of the 32-bit data bus. A 32-bit external I/O device is accessed: This is the byte enable signal for DATA(31:24) of the 32-bit data bus. ...
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... This is the 18.432 MHz oscillator’s input pin connected to one side of a crystal resonator. CLKX2 Output This is the 18.432 MHz oscillator’s output pin connected to one side of a crystal resonator. FIRCLK Input This is the 48 MHz clock input pin. This signal inputs a clock when FIR is used. ...
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Battery monitor interface signals Signal I/O BATTINH/ Input The function differs depending on the setting of the MPOWER pin. BATTINT# • When MPOWER = 0 BATTINH function This signal enables/disables activation at power-on. 1: Activation enabled 0: Activation disabled ...
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RS-232-C interface signals Signal I/O RxD Input This is a receive data signal used when the RS-232-C controller sends serial data to the V 4122. R CTS# Input This is a transmit enable signal. Assert this signal ...
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Debug serial interface signals Signal I/O DDIN/GPIO34 I/O Debug serial data input signal used when serial data is transferred from the external serial controller to the V This signal can be used as a general-purpose output port ...
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Clocked serial signals Signal I/O SIN Input Clocked serial input signal SOUT Output Clocked serial output signal SECLK Output Synchronous clock output for the clocked serial interface (10) General-purpose I/O signals Signal I/O GPIO(3:0) I/O Maskable activation factor input ...
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PCI Like bus interface signals Signal I/O AD(31:0) I/O This is a 32-bit address bus and data bus. In the address phase, addresses are output, and in the data phase, data is output. CBE(3:0) I/O These are the bus-command/byte-enable ...
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... JTDI/RMODE# Input This is the RMODE#/JTDI alternate function pin. When JTRST# is active, it functions as RMODE#, and when JTRST# is inactive, it functions as JTDI debugging tool is not connected externally, pull up to high level. • RMODE#: Input When JTRST# is active, this becomes the reset mode pin. The debug reset initial value is determined according to the level of this signal ...
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Signal I/O NWIREEN/ I/O The function differs depending on the operating status. • During RTC reset (input) HLDAK# NWIREEN: This signal is sampled when the RTCRST# signal changes from low level to high Products of version 3.1: This signal controls ...
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Pin Status in Specific States Pin Name When Reset by RTC AD(31:0) 0 ADD(24:1) 0 BATTINH/BATTINT# Hi-Z BKTGIO# 1 CAS 0 CBE(3:0) 0 CKE(1:0) 0 CLKOUT 0 CLKRUN Hi-Z CS(1:0)# Hi-Z CS2#/ROMCS2# Hi-Z CS3#/ROMCS3# Hi-Z CTS# Hi-Z DATA(15:0) 0 ...
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Pin Name When Reset by RTC DATA(31:16)/GPIO(31:16) Note 1 DCD#/GPIO15 Hi-Z DCTS#/GPIO35 Hi-Z DDIN/GPIO34 Hi-Z DDOUT/DBUS32/GPIO32 Hi-Z DEVSEL# Hi-Z DQM(3:0) Hi-Z DRTS#/MIPS16EN/GPIO33 Hi-Z DSR# Hi-Z DTR#/CLKSEL0 Hi-Z Note 9 FIRCLK Hi-Z Note 9 FIRDIN#/SEL Hi-Z FRAME# Hi-Z Notes 1. When ...
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Pin Name When Reset by RTC GNT(2:0)# Hi-Z GPIO(5:0) Hi-Z GPIO6/SYSDIR 0 GPIO(13:7) Hi-Z IOCS(1:0)# Hi-Z IORDY Hi-Z Note 4 IRDIN Hi-Z Note 4 IRDOUT# 0 IRDY# Hi-Z JTCK Hi-Z JTDI/RMODE# Hi-Z JTDO Hi-Z JTMS Hi-Z JTRST# Hi-Z LEDOUT# Hi-Z ...
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Pin Name When Reset by RTC REQ(2:0)# Hi-Z ROMCS(1:0)# Hi-Z RST# 0 RSTSW# Hi-Z RTCRST# Hi-Z RTS#/CLKSEL1 Hi-Z RxD Hi-Z SCLK 0 SECLK 0 SERR# Hi-Z SIN Hi-Z SOUT 0 SPOWER 0 STOP# Hi-Z SWR# Hi-Z HLDRQ# Hi-Z NWIREEN/HLDAK# Hi-Z ...
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... Pull-up processing is recommended for expansion to the next model. Remarks 1. External handling is not required for the pins with no special directions in the Pin Handling column (−). 2. For the pins with no special directions in the Recommended Connection of Unused Pins column, follow the directions in Pin Handling column. ...
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... LEDOUT# pin has to be pulled up regardless of whether the LED function is being used. Remarks 1. External handling is not required for the pins with no special directions in the Pin Handling column (−). 2. For the pins with no special directions in the Recommended Connection of Unused Pins column, follow the directions in Pin Handling column. ...
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Pin I/O Circuits Type A V Data P-ch Output N-ch disable Input enable Type B DD Data IN/OUT Open drain Output disable Data Sheet U15585EJ3V0DS µ µ µ µ PD30122 V DD P-ch IN/OUT N-ch 23 ...
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ELECTRICAL SPECIFICATIONS = 25° ° ° ° C) Absolute Maximum Ratings (T A Parameter Symbol Supply voltage V Applies to V DD1 V Applies to CV DD3 Input voltage DD3 V DD3 Storage temperature T stg ...
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Operating Conditions (1) 150 MHz model Parameter Symbol Supply voltage V DD1 V DD3 Ambient temperature T A Note 1 Oscillation start voltage V DDS Note 2 Oscillation hold voltage V DDH1 Note 3 Oscillation hold voltage V DDH2 Notes ...
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DC Characteristics = − − − − +85° ° ° ° (1) 150 MHz model (T A Parameter Symbol Output voltage, high V OH1 Output voltage, low V OL1 Note 1 Clock input voltage, high V ...
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Parameter Symbol Note 2 Supply current I In Fullspeed mode DD1 In Standby mode In Suspend mode In Hibernate mode, V when LED unit is off. Note Fullspeed mode DD3 In Standby mode In Suspend mode In ...
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C, V (2) 180 MHz model (T A Parameter Symbol Output voltage, high V OH1 Output voltage, low V OL1 Note 1 Clock input voltage, high V IH1 Note ...
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Parameter Symbol Note 2 Supply current I In Fullspeed mode DD1 In Standby mode In Suspend mode In Hibernate mode, V when LED unit is off. Note Fullspeed mode DD3 In Standby mode In Suspend mode In ...
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C) Data Retention Characteristics (T A Parameter Note Data retention voltage Data retention input voltage, high Note The data retention voltage is the voltage at which the operation of the ElapsedTime counter and the data ...
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C) AC Characteristics ( test input waveform (a) DATA(15:0), DATA(31:16)/GPIO(31:16), IORDY, RxD, CTS#, DSR#, TxD/CLKSEL2, FIRCLK, RTS#/ CLKSEL1, DTR#/CLKSEL0, IRDIN, FIRDIN#/SEL, DDIN/GPIO34, DCTS#/GPIO35, DDOUT/DBUS32/ GPIO32, AD(31:0), CBE(3:0), ...
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Load conditions Note (a) SCLK, ADD(24:10) , ADD(4:1), CKE(1:0), DQM(3:0), ROMCS(1:0)#, CS(3:2)#/ROMCS(3:2)#, CS(1:0)#, DATA(31:16)/GPIO(31:16), DATA(15:0), RAS Note SCLK, ADD(24:10) , ADD(4:1), CKE(1:0), DQM(3:0), ROMCS(1:0)#, CS(3:2)#/ROMCS(3:2)#, CS(1:0)#, DATA(31:16)/GPIO(31:16), DATA(15:0), RAS Note SWR# Note The ADD(24:10), RAS, CAS, and SWR# pins are ...
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Clock parameter Parameter Symbol Note 1 FIRCLK clock frequency f FIRCYC1 f FIRCYC2 Note 1 FIRCLK clock duty t FIRDUTY Note 2 SCLK high-level width t CH Note 2 SCLK low-level width t CL Note 3 SCLK jitter t ...
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Reset parameter Parameter Symbol Reset input low-level width t WRSL RTCRST# (input) Remark For the RTCRST# characteristics at power application, refer to V (3) Initialization parameter Parameter Symbol Data sampling time t SS (from RTCRST# ↑) Output delay time ...
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GPIO interface parameter (1/2) Parameter Symbol Note 1 Input level width t INP1 GPIO input rise time t GPINR1 t GPINR2 GPIO input fall time t GPINF1 t GPINF2 Output level width t OUTP Notes 1. The N value ...
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GPIO interface parameter (2/2) (a) Input level width Note GPIO(5:0), SYSDIR/GPIO6, GPIO(13:7), DATA(31:16)/GPIO(31:16) pins (b) GPIO input rise/fall time Notes 1. GPIO(5:0), SYSDIR/GPIO6, GPIO(13:7) pins 2. DATA(31:16)/GPIO(31:16) pins (c) Output level width Note GPIO(5:0), SYSDIR/GPIO6, GPIO(13:7), DATA(31:16)/GPIO(31:16), DDOUT/DBUS32/GPIO32, DRTS#/MIPS16EN/GPIO33, ...
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Normal ROM parameter (1/2) Parameter Note Data access time (from address) Data access time (from ROMCS(3:0)# ↓) Note Data access time (from RD# ↓) Note Data input setup time Data input hold time Note The value ...
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Normal ROM parameter (2/2) ADD(24:1) (output) ROMCS(3:0)# (output) RD# (output) DATA Invalid (I/O) Remark The broken lines indicate high impedance ACC Data Sheet U15585EJ3V0DS µ µ µ µ PD30122 ...
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Page ROM parameter (1/2) Parameter Note Data access time (from address) Data access time (from ROMCS(3:0)# ↓) Note Data access time (from RD# ↓) Note Data input setup time Data input hold time Note The value ...
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Page ROM parameter (2/2) ADD(24:1) (output) ROMCS(3:0)# (output) RD# (output) DATA Invalid (I/O) Remark The broken lines indicate high impedance ACC2 ACC1 Data Sheet ...
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Flash memory mode write parameter Parameter Write cycle time Address setup time (to WR# ↑) Address setup time (to ROMCS(3:0)# ↓) ROMCS(3:0)# setup time (to WR# ↓) WR# low-level width ROMCS(3:0)# hold time (from WR# ↑) Address hold time ...
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Flash memory mode read parameter Parameter Data output delay time from address Data output delay time from ROMCS(3:0)# Address setup time (to ROMCS(3:0)# ↓) Data output delay time from RD# ↓ Address setup time (to RD# ↓) ROMCS(3:0)# hold ...
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I/O (LCD) interface parameter (1/2) Parameter Address setup time (to command signal ↓) Note 1, 2 Address hold time (from command signal ↑) Note 1, 2 Note 1, 2 Command signal recovery time Note 2 IORDY sampling start time ...
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I/O (LCD) interface parameter (2/2) VTDIV(2:0) 000 001 CLKSEL(2:0) 111 RFU RFU 110 RFU RFU 101 RFU RFU 100 33.2 RFU 011 31.0 RFU 010 29.9 RFU 001 33.2 RFU 000 38.2 RFU ADD(24:1) (output) DQM(3:0) (output) IOCS0#, IOCS1# ...
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Bus hold parameter (1/3) Parameter Symbol Note HLDRQ# input pulse width t HP Data floating delay time t OFF Data valid delay time t ON Note When the V 4122 receives an input signal of less than 271 ns, ...
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Bus hold parameter (2/3) (b) Releasing bus hold (HLDRQ#) CLKX1 (input) HLDRQ# (input) HLDAK# (output) Note Note Applies to the following pins. • ADD(24:1), DATA(15:0), CKE(1:0), DQM(3:0), CS(1:0)#, RAS, CAS, SCLK, RD#, WR#, and SWR# pins • SYSDIR/GPIO6 pin ...
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Bus hold parameter (3/3) (c) Releasing bus hold (RSTSW#) RTCX1 (input) CLKX1 (input) Sampling RSTSW# (input) HLDRQ# (input) HLDAK# (output) Note Note Applies to the following pins. • ADD(24:1), DATA(15:0), CKE(1:0), DQM(3:0), CS(1:0)#, RAS, CAS, SCLK, RD#, WR#, and ...
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Serial interface parameter (1/2) Parameter Note TxD output pulse width Note RxD input pulse width Note IRDOUT# high-level output pulse width IRDIN input pulse width Note N indicates the data transfer rate per bit, which is determined by the ...
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Serial interface parameter (2/2) TxD (output) RxD (input) IRDOUT# (output) IRDIN (input) t TXD t RXD t IRDOUT t IRDIN Data Sheet U15585EJ3V0DS µ µ µ µ PD30122 49 ...
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Debug serial interface parameter Parameter Note DDOUT output pulse width Note DDIN input pulse width Note N indicates the data transfer rate per bit, which is determined by the divisor of the baud rate generator set with the DSIUDLL ...
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SDRAM interface parameter (1/2) Parameter Note SCLK jitter SCLK high-level width SCLK low-level width Output delay time (from SCLK ↑) Output delay time (from SCLK ↓) Data input setup time Data input hold time Note Precision tests have not ...
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SDRAM interface parameter (2/ SCLK (output) t DSP CKE(1:0) (output) t DSP Note 1 t DSN ADD(24:10) (output) t DSN RAS (output) CAS, SWR# (output) Note 2 DQM (output) Note 3 DATA (output) Note 3 ...
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CSI (clocked serial interface) parameter Parameter Operating frequency SECLK clock cycle time SECLK high-level width SECLK low-level width SECLK rise time SECLK fall time SIN input setup time (to SECLK ↑) SIN input hold time (from SECLK ↑) SOUT ...
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PCI like bus interface parameter (1/2) Parameter Notes 1, 2 PCLK clock cycle Notes 1, 2 PCLK high-level width Notes 1, 2 PCLK low-level width Output valid delay time (from PCLK ↑) Note 3 Delay time from floating to ...
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PCI like bus interface parameter (2/2) t CLKH PCLK (output) t VAL Note 1 t OFF Note 2 Note 2 Note 3 Notes 1. Applies to the AD(31:0), CBE(3:0), DEVSEL#, FRAME#, IRDY#, LOCK#, PAR, PERR#, SERR#, STOP#, TRDY#, GNT(2:0)#, ...
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PACKAGE DRAWING 224-PIN PLASTIC FBGA (16x16 Index mark ...
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... The µ PD30122 should be soldered and mounted under the following recommended conditions. For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. Table 4-1. Surface Mounting Type Soldering Conditions µ ...
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... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...
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... Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • ...
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... NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such NEC Electronics products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others ...