A42MX09-PQ100I Actel, A42MX09-PQ100I Datasheet
A42MX09-PQ100I
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A42MX09-PQ100I Summary of contents
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... Up to 100% Resource Utilization and 100% Pin Locking • Deterministic, User-Controllable Timing • Unique In-System Capability with Silicon Explorer II • Low Power Consumption • IEEE Standard 1149.1 (JTAG) Boundary Scan Testing A40MX04 A42MX09 A42MX16 6,000 14,000 24,000 – – – 348 ...
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... PLCC PLCC PLCC Device 44-Pin 68-Pin 84-Pin A40MX02 34 57 A40MX04 34 57 A42MX09 – – A42MX16 – – A42MX24 – – A42MX36 – – Note: Package Definitions PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, VQFP = Very Thin Quad Flat Pack, ...
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... Note: Refer to the 40MX and 42MX Automotive Family FPGAs Contact your local Actel representative for device availability. CQFP 256-Pin 202 A40MX04 A42MX09 A42MX16 ...
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Table of Contents 40MX and 42MX FPGA Families General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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FPGA Families Table of Contents 100-Pin PQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... MX devices provide performance up to 250 MHz, are live on power-up and have one-fifth the standby power consumption of comparable FPGAs. Actel’s MX FPGAs provide up to 202 user I/Os and are available in a wide variety of packages and speed grades. Actel’s A42MX24 and A42MX36 devices also feature ...
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FPGA Families The 42MX devices contain three types of logic modules: combinatorial (C-modules), sequential (S-modules) and decode (D-modules). Figure 1-2 combinatorial logic module. The S-module, shown in Figure 1-3, implements the same combinatorial logic function as the ...
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... The A42MX36 dual-port SRAM blocks provide an optimal solution for high-speed buffered applications requiring FIFO and LIFO queues. The ACTgen Macro Builder within Actel's Designer software provides capability to quickly design memory functions with the SRAM blocks. Unused SRAM blocks can be used to implement registers for other user logic within the design ...
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FPGA Families Routing Structure The MX architecture uses vertical and horizontal routing tracks to interconnect the various logic and I/O modules. These routing tracks are metal interconnects that may be continuous or split into segments. Varying segment ...
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Figure 1-7 • Clock Networks of 42MX Devices QCLKA QCLKB *QCLK1IN *QCLK2IN Note: *QCLK1IN, QCLK2IN, QCLK3IN, and QCLK4IN are internally-generated signals. Figure 1-8 • Quadrant Clock Network of A42MX36 Devices CLKB CLKINB CLKA CLKINA From S0 Pads Internal CLKMOD Signal ...
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... The I/O module can be used to latch input or output data, or both, providing fast set-up time. In addition, the Actel Designer software tools can build a D- type flip-flop using a C-module combined with an I/O module to register input and output signals. Refer to the Antifuse Macro Library Guide for more details ...
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... The procedure for programming an MX device using Silicon Sculptor follows: 1. Load the .AFM file 2. Select the device to be programmed 3. Begin programming When the design is ready production, Actel offers device through Programming from the factory. multi-site ...
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... Equivalent capacitance is frequency-independent, so the results can be used over a wide range of operating conditions. Equivalent capacitance values are shown below. C Values for Actel MX FPGAs EQ Modules (C Input Buffers (C Output Buffers (C Routed Array Clock Buffer Loads (C To calculate the active power dissipated from the complete design, the switching frequency of each part of the logic must be known ...
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... Fixed Capacitance Values for MX FPGAs (pF Device Type routed_Clk1 A40MX02 41.4 A40MX04 68.6 A42MX09 118 A42MX16 165 A42MX24 185 A42MX36 220 Test Circuitry and Silicon Explorer II Probe MX devices contain probing circuitry that provides built- in access to every node in a design, via the use of Silicon Explorer II ...
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FPGA Families Serial Connection to Windows PC Figure 1-13 • Silicon Explorer II Setup with 42MX Table 2 • Device Configuration Options for Probe Capability Security Fuse(s) Programmed No No Yes Notes: 1. Avoid using SDI, SDO, ...
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Each I/O cell has three boundary-scan register cells, each with a serial-in, serial-out, parallel-in, and parallel-out pin. The serial pins are used to serially connect all the boundary-scan register cells in a device into a boundary- scan register chain, which ...
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... Format Description application note. Actel BSDL files are grouped into two categories - generic and device-specific. The generic files assign all user I/Os as inouts. Device-specific files assign user I/Os as inputs, outputs or inouts. Generic files for MX devices are available on Actel's website at http://www.actel.com/techdocs/models/bsdl.html. v6.0 Unchecked User I/O User I/O ...
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... Development Tool Support The MX family of FPGAs is fully supported by both Actel's Libero™ Integrated Design Environment and Designer FPGA Development software. Actel Libero IDE is a design management environment that streamlines the design flow. Libero IDE provides an integrated design manager that seamlessly integrates design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools ...
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FPGA Families 5.0V Operating Conditions Table 6 • Absolute Maximum Ratings for 40MX Devices* Symbol V DC Supply Voltage CC V Input Voltage I V Output Voltage O t Storage Temperature STG Note: *Stresses beyond those listed ...
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... IN Input Transition Time, T and I/O Capacitance IO Standby Current, A40MX02 A40MX04 CC A42MX09 A42MX16 A42MX24, A42MX36 Low-Power Mode 42MX devices Standby Current only I , I/O source sink Can be derived from the IO current Notes: 1. Only one output tested at a time All outputs unloaded. All inputs = V ...
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FPGA Families 3.3V Operating Conditions Table 10 • Absolute Maximum Ratings for 40MX Devices* Symbol Parameter V DC Supply Voltage CC V Input Voltage I V Output Voltage O t Storage Temperature STG Note: *Stresses beyond those ...
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... Input Transition Time, T and I/O Capacitance IO 2 Standby Current, I A40MX02, CC A40MX04 A42MX09 A42MX16 A42MX24, A42MX36 Low-Power Mode 42MX Standby Current devices only I , I/O source sink Can be derived from the IO current Notes: 1. Only one output tested at a time All outputs unloaded. All inputs = V ...
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... Input Transition Time, T and I/O Capacitance IO 2 Standby Current, I A42MX09 CC A42MX16 A42MX24, A42MX36 Low-Power Mode Standby Current I I/O source sink current Can be derived from the IO Notes: 1. Only one output tested at a time. V CCI 2. All outputs unloaded. All inputs = Parameter – ...
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Output Drive Characteristics for 5.0V PCI Signaling MX PCI device I/O drivers were designed specifically for high-performance PCI systems. the typical output drive characteristics of the MX devices. MX output drivers are compliant with the PCI Local Bus Specification. Table ...
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FPGA Families Output Drive Characteristics for 3.3V PCI Signaling Table 19 • DC Specification (3.3V PCI Signaling) Symbol Parameter V Supply Voltage for I/Os CCI V Input High Voltage IH V Input Low Voltage IL I Input ...
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MX PCI I 0.15 0.10 0.05 0. –0.05 PCI I Maximum OH –0.10 –0.15 –0.20 Figure 1-16 • Typical Output Drive Characteristics (Based Upon Measured Data) PCI I Maximum OL OL ...
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FPGA Families Junction Temperature (T The temperature variable in the Designer software refers to the junction temperature, temperature. This is an important distinction because the heat generated from dynamic power consumption is usually hotter than the ambient ...
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... G t INH=0 INSU=0 INGL=1.3 ns Array Clocks t CKH=2. MAX=296 MHz Notes: *Values are shown for A42MX09 ‘–3’ at 5.0V worst-case commercial conditions. † Input module predicted routing delay. Figure 1-18 • 42MX Timing Model* Predicted Internal Delays Routing Delays IRD2=2.59 ns Logic Module t IRD1=2 ...
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FPGA Families Input Delays I/O Module t INYL=0 INH=0 INSU=0 INGL=1.3 ns Array Clocks t CKH=2. MAX=296 MHz Notes: * Values are shown for A42MX36 ‘–3’ ...
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Parameter Measurement In 50% 50 PAD 1. DLH t DHL Figure 1-21 • Output Buffer Delays Load 1 (Used to measure propagation delay) To the output under test Figure 1-22 • AC Test Loads PAD ...
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FPGA Families Sequential Module Timing Characteristics D* G, CLK E Q PRE, CLR Note: *D represents all data functions involving A, B, and S for multiplexed flip-flops. Figure 1-25 • Flip-Flops and Latches PRE ...
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Sequential Timing Characteristics CLK Figure 1-26 • Input Buffer Latches D G Figure 1-27 • Output Buffer Latches PAD DATA IBDL G PAD DATA G t INSU CLK t SU EXT D PAD OBDLHS G t OUTSU t OUTH v6.0 ...
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FPGA Families Decode Module Timing A– Figure 1-28 • Decode Module Timing SRAM Timing Characteristics Figure 1-29 • SRAM Timing Characteristics Dual-Port SRAM Timing Waveforms WD[7:0] WRAD[5:0] Note: ...
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RCLK REN RDAD[5:0] RD[7:0] Note: Identical timing for falling edge clock. Figure 1-31 • 42MX SRAM Synchronous Read Operation RDAD[5:0] RD[7:0] Figure 1-32 • 42MX SRAM Asynchronous Read Operation—Type 1 (Read Address Controlled) WEN WD[7:0] WRAD[5:0] BLKEN WCLK RD[7:0] Figure ...
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... Critical net delays can then be applied to the most timing critical paths. Critical nets are determined by net property assignment in Actel's Designer software prior to placement and routing the nets in a design may be designated as critical. ...
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Temperature and Voltage Derating Factors Table 22 • 42MX Temperature and Voltage Derating Factors (Normalized 25° 42MX Voltage –55°C 4.50 0.93 4.75 0.88 5.00 0.85 5.25 0.84 5.50 0.83 1.50 1.40 1.30 1.20 1.10 1.00 ...
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FPGA Families Table 23 • 40MX Temperature and Voltage Derating Factors (Normalized 25° 40MX Voltage –55°C 4.50 0.89 4.75 0.84 5.00 0.82 5.25 0.80 5.50 0.79 1.50 1.40 1.30 1.20 1.10 1.00 ...
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Table 24 • 42MX Temperature and Voltage Derating Factors (Normalized 25° 42MX Voltage –55°C 3.00 0.97 3.30 0.84 3.60 0.81 1.60 1.50 1.40 1.30 1.20 1.10 1.00 0.90 0.80 0.70 0.60 0.50 0.40 3.00 Note: ...
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FPGA Families Table 25 • 40MX Temperature and Voltage Derating Factors (Normalized 25° 40MX Voltage –55°C 3.00 1.08 3.30 0.86 3.60 0.83 2.20 2.00 1.80 1.60 1.40 1.20 1.00 0.80 0.60 3.00 ...
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... GNT# has a setup of 10; REW# has a setup of 12. 40MX and 42MX FPGA Families PCI Models Actel provides synthesizable VHDL and Verilog-HDL models for a PCI Target interface, a PCI Target and Target+DMA Master interface. Contact your Actel sales representative for more details. PCI A42MX24 Min. ...
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FPGA Families Timing Characteristics Table 28 • A40MX02 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, V Parameter Description Logic Module Propagation Delays t Single Module PD1 t Dual-Module Macros PD2 t Sequential Clock-to Latch ...
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Table 28 • A40MX02 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description Input Module Predicted Routing Delays t FO=1 Routing Delay IRD1 t FO=2 Routing Delay IRD2 t FO=3 Routing Delay IRD3 t FO=4 Routing Delay ...
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FPGA Families Table 28 • A40MX02 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description 4 TTL Output Module Timing t Data-to-Pad HIGH DLH t Data-to-Pad LOW DHL t Enable Pad Z to ENZH ...
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Table 29 • A40MX02 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions, V Parameter Description Logic Module Propagation Delays t Single Module PD1 t Dual-Module Macros PD2 t Sequential Clock-to Latch G-to Flip-Flop (Latch) Reset-to-Q RS ...
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FPGA Families Table 29 • A40MX02 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description Input Module Predicted Routing Delays t FO=1 Routing Delay IRD1 t FO=2 Routing Delay IRD2 t FO=3 Routing Delay ...
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Table 29 • A40MX02 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description 4 CMOS Output Module Timing t Data-to-Pad HIGH DLH t Data-to-Pad LOW DHL t Enable Pad Z to HIGH ENZH t Enable Pad Z ...
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FPGA Families Table 30 • A40MX04 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, V Parameter Description Logic Module Propagation Delays t Single Module PD1 t Dual-Module Macros PD2 t Sequential Clock-to Latch G-to-Q GO ...
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Table 30 • A40MX04 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description Input Module Predicted Routing Delays t FO=1 Routing Delay IRD1 t FO=2 Routing Delay IRD2 t FO=3 Routing Delay IRD3 t FO=4 Routing Delay ...
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FPGA Families Table 30 • A40MX04 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description 1 CMOS Output Module Timing t Data-to-Pad HIGH DLH t Data-to-Pad LOW DHL t Enable Pad Z to HIGH ...
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Table 31 • A40MX04 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions, V Parameter Description Logic Module Propagation Delays t Single Module PD1 t Dual-Module Macros PD2 t Sequential Clock-to Latch G-to Flip-Flop (Latch) Reset-to-Q RS ...
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FPGA Families Table 31 • A40MX04 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description Input Module Predicted Routing Delays t FO=1 Routing Delay IRD1 t FO=2 Routing Delay IRD2 t FO=3 Routing Delay ...
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Table 31 • A40MX04 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description 4 CMOS Output Module Timing t Data-to-Pad HIGH DLH t Data-to-Pad LOW DHL t Enable Pad Z to HIGH ENZH t Enable Pad Z ...
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... FPGA Families Table 32 • A42MX09 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, V Parameter Description Logic Module Propagation Delays t Single Module PD1 t Sequential Clock-to Latch G-to Flip-Flop (Latch) Reset-to-Q RS Logic Module Predicted Routing Delays t FO=1 Routing Delay RD1 t FO=2 Routing Delay ...
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... Table 32 • A42MX09 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description Input Module Propagation Delays t Pad-to-Y HIGH INYH t Pad-to-Y LOW INYL HIGH INGH LOW INGL Input Module Predicted Routing Delays t FO=1 Routing Delay IRD1 t FO=2 Routing Delay ...
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... FPGA Families Table 32 • A42MX09 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description 5 TTL Output Module Timing t Data-to-Pad HIGH DLH t Data-to-Pad LOW DHL t Enable Pad Z to HIGH ENZH t Enable Pad Z to LOW ENZL t Enable Pad HIGH to Z ...
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... Table 32 • A42MX09 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description 5 CMOS Output Module Timing t Data-to-Pad HIGH DLH t Data-to-Pad LOW DHL t Enable Pad Z to HIGH ENZH t Enable Pad Z to LOW ENZL t Enable Pad HIGH to Z ENHZ t Enable Pad LOW to Z ...
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... FPGA Families Table 33 • A42MX09 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions, V Parameter Description Logic Module Propagation Delays t Single Module PD1 t Sequential Clock-to Latch G-to Flip-Flop (Latch) Reset-to-Q RS Logic Module Predicted Routing Delays t FO=1 Routing Delay RD1 t FO=2 Routing Delay ...
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... Table 33 • A42MX09 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description Input Module Propagation Delays t Pad-to-Y HIGH INYH t Pad-to-Y LOW INYL HIGH INGH LOW INGL Input Module Predicted Routing Delays t FO=1 Routing Delay IRD1 t FO=2 Routing Delay ...
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... FPGA Families Table 33 • A42MX09 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description 5 TTL Output Module Timing t Data-to-Pad HIGH DLH t Data-to-Pad LOW DHL t Enable Pad Z to ENZH HIGH t Enable Pad Z to ENZL LOW t Enable Pad HIGH to ...
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... Table 33 • A42MX09 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description 5 CMOS Output Module Timing t Data-to-Pad HIGH DLH t Data-to-Pad LOW DHL t Enable Pad Z to HIGH ENZH t Enable Pad Z to LOW ENZL t Enable Pad HIGH to Z ENHZ t Enable Pad LOW to Z ...
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FPGA Families Table 34 • A42MX16 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, V Parameter Description Logic Module Propagation Delays t Single Module PD1 t Sequential Clock-to Latch G-to Flip-Flop (Latch) Reset-to-Q ...
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Table 34 • A42MX16 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description Input Module Propagation Delays t Pad-to-Y HIGH INYH t Pad-to-Y LOW INYL HIGH INGH LOW INGL ...
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FPGA Families Table 34 • A42MX16 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description 5 TTL Output Module Timing t Data-to-Pad HIGH DLH t Data-to-Pad LOW DHL t Enable Pad Z to HIGH ...
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Table 35 • A42MX16 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions, V Parameter Description Logic Module Propagation Delays t Single Module PD1 t Sequential Clock-to Latch G-to Flip-Flop (Latch) Reset-to-Q RS Logic Module Predicted Routing ...
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FPGA Families Table 35 • A42MX16 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description Input Module Propagation Delays t Pad-to-Y HIGH INYH t Pad-to-Y LOW INYL HIGH INGH t ...
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Table 35 • A42MX16 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description 5 TTL Output Module Timing t Data-to-Pad HIGH DLH t Data-to-Pad LOW DHL t Enable Pad Z to HIGH ENZH t Enable Pad Z ...
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FPGA Families Table 36 • A42MX24 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, V Parameter Description Logic Module Combinatorial Functions t Internal Array Module Delay PD t Internal Decode Module Delay PDD Logic Module Predicted Routing ...
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Table 36 • A42MX24 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description Input Module Predicted Routing Delays t FO=1 Routing Delay IRD1 t FO=2 Routing Delay IRD2 t FO=3 Routing Delay IRD3 t FO=4 Routing Delay ...
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FPGA Families Table 36 • A42MX24 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description 5 TTL Output Module Timing t Data-to-Pad HIGH DLH t Data-to-Pad LOW DHL t Enable Pad Z to HIGH ...
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Table 36 • A42MX24 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description 5 CMOS Output Module Timing t Data-to-Pad HIGH DLH t Data-to-Pad LOW DHL t Enable Pad Z to HIGH ENZH t Enable Pad Z ...
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FPGA Families Table 37 • A42MX24 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions, V Parameter Description Logic Module Combinatorial Functions t Internal Array Module Delay PD t Internal Decode Module Delay PDD Logic Module Predicted Routing ...
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Table 37 • A42MX24 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description Input Module Predicted Routing Delays t FO=1 Routing Delay IRD1 t FO=2 Routing Delay IRD2 t FO=3 Routing Delay IRD3 t FO=4 Routing Delay ...
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FPGA Families Table 37 • A42MX24 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description 5 TTL Output Module Timing (Continued) t I/O Latch Output Hold LH t I/O Latch Clock-to-Out LCO (Pad-to-Pad) 32 ...
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Table 38 • A42MX36 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, V Parameter Description Logic Module Combinatorial Functions t Internal Array Module Delay PD t Internal Decode Module Delay PDD Logic Module Predicted Routing Delays t FO=1 Routing Delay ...
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FPGA Families Table 38 • A42MX36 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, V Parameter Description Synchronous SRAM Operations (Continued) t Address/Data Hold Time ADH t Read Enable Set-Up RENSU t Read Enable Hold RENH t ...
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Table 38 • A42MX36 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, V Parameter Description Input Module Predicted Routing Delays t FO=1 Routing Delay IRD1 t FO=2 Routing Delay IRD2 t FO=3 Routing Delay IRD3 t FO=4 Routing Delay IRD4 ...
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FPGA Families Table 38 • A42MX36 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, V Parameter Description 5 TTL Output Module Timing (Continued) t Enable Pad LOW to Z ENLZ t G-to-Pad HIGH GLH t G-to-Pad LOW ...
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Table 39 • A42MX36 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions, V Parameter Description Logic Module Combinatorial Functions t Internal Array Module Delay PD t Internal Decode Module Delay PDD Logic Module Predicted Routing Delays t FO=1 Routing Delay ...
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FPGA Families Table 39 • A42MX36 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description Synchronous SRAM Operations (Continued) t Address/Data Hold Time ADH t Read Enable Set-Up RENSU t Read Enable Hold RENH ...
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Table 39 • A42MX36 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description Input Module Predicted Routing Delays t FO=1 Routing Delay IRD1 t FO=2 Routing Delay IRD2 t FO=3 Routing Delay IRD3 t FO=4 Routing Delay ...
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FPGA Families Table 39 • A42MX36 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description 5 TTL Output Module Timing t Enable Pad LOW to Z ENLZ t G-to-Pad HIGH GLH t G-to-Pad LOW ...
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... CMOS specifications. Unused I/Os pins are configured by the Designer software as shown in Table 40 • Configuration of Unused I/Os Device A40MX02, A40MX04 A42MX09, A42MX16 A42MX24, A42MX36 In all cases recommended to tie all unused MX I/O pins to LOW on the board. This applies to all dual- purpose pins when configured as I/Os as well. LP Low Power Mode Controls the low power mode of all 42MX devices ...
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FPGA Families TMS, I/O Test Mode Select The TMS pin controls the use of the IEEE 1149.1 Boundary Scan pins (TCK, TDI, TDO). In flexible mode when the TMS pin is set LOW, the TCK, TDI and ...
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Package Pin Assignments 44-Pin PLCC Figure 2-1 • 44-Pin PLCC 44-pin PLCC Pin Number A40MX02 Function A40MX04 Function 1 I I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 GND 11 ...
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FPGA Families 68-Pin PLCC Figure 2-2 • 68-Pin PLCC 44-pin PLCC Pin A40MX02 A40MX04 Number Function Function 1 I/O I/O 2 I/O I/O 3 I/O I I/O I/O 6 I/O I/O ...
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PLCC Figure 2-3 • 84-Pin PLCC 40MX and 42MX FPGA Families 1 84 84-Pin PLCC v6.0 2-3 ...
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... I/O I/O 49 I/O I/O 50 I/O I/O 51 I/O I/O 52 I/O I/O 53 I/O I/O 54 I/O I/O 55 I/O I CCI CCI CCA CCA I/O I/O 59 I/O I/O 60 I/O I/O 61 I/O I/O 62 GND GND 63 I/O I/O 64 I/O I/O 65 I/O I/O 66 I/O I/O 67 I/O I/O 68 I/O TMS, I/O 69 I/O TDI, I/O 70 v6.0 84-Pin PLCC A40MX04 A42MX09 A42MX16 A42MX24 Function Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I CCA CCA I/O I/O I/O I/O I/O I/O V I/O I/O CC I/O I/O I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O I/O I/O SDO, I/O SDO, I/O SDO, TDO, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
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... SDI, I/O I/O 73 DCLK, I/O I/O 74 PRA, I/O I/O 75 PRB, I/O I/O 76 I/O SDI, I/O SDI, I/O 77 I/O I/O A42MX24 Pin A40MX04 Function Number I/O I/O 78 I/O I/O 79 I/O I/O 80 I/O I/O 81 I/O I/O 82 SDI, I/O 83 I/O I/O 84 v6.0 40MX and 42MX FPGA Families 84-Pin PLCC A42MX09 A42MX16 A42MX24 Function Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRA, I/O PRA, I/O GND I/O I/O I/O CLKA, I/O CLKA, I/O CLKA, I/O I CCA CCA WD, I/O WD, I/O WD, I/O PRA, I/O I/O V CCA 2-5 ...
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FPGA Families 100-Pin PQFP Package 100 1 Figure 2-4 • 100-Pin PQFP Package (Top View 100-Pin PQFP v6.0 ...
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... I/O I/O 53 I/O I/O 54 I/O I/O 55 I/O I/O 56 GND GND 57 I/O I/O 58 I/O I/O 59 I/O I/O 60 I/O I/O 61 I/O I/O 62 I/O I/O 63 I/O I/O 64 I/O I/O 65 I/O I/O 66 I/O I/O 67 I/O I/O 68 GND GND 69 I/O I/O 70 v6.0 40MX and 42MX FPGA Families 100-Pin PQFP A40MX02 A40MX04 A42MX09 A42MX16 Function Function Function Function GND GND I/O GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O V CCA I/O I/O I/O I/O I I/O I/O I/O I/O I/O GND I/O I/O I/O NC I/O I/O NC I/O I/O NC I/O I I/O NC ...
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... GND 87 I/O I/O 88 I/O I/O 89 I/O I/O 90 I/O I/O 91 I/O I/O 92 I/O I/O 93 SDI, I/O SDI, I/O 94 I/O I/O 95 I/O I/O 96 I/O I/O 97 I/O I/O 98 GND GND 99 I/O I/O 100 v6.0 100-Pin PQFP A40MX02 A40MX04 A42MX09 A42MX16 Function Function Function Function GND GND I/O GND GND PRA, I/O I/O I/O I/O I/O I/O CLKA, I/O CLKA, I/O CLK, I/O CLK, I/O V CCA I/O I/O I/O MODE MODE CLKB PRB, I I/O I/O NC I/O GND ...
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PQFP Package 160 1 Figure 2-5 • 160-Pin PQFP Package (Top View) 40MX and 42MX FPGA Families 160-Pin PQFP v6.0 2-9 ...
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... PRB, I/O 51 I/O 52 CLKB, I CCA CLKA, I/O 56 I/O 57 PRA, I/O 58 WD, I/O 59 WD, I/O 60 I/O 61 I/O 62 I/O 63 WD, I/O 64 GND 65 WD, I/O 66 I/O 67 I CCI CCI v6.0 160-Pin PQFP A42MX09 A42MX16 A42MX24 Function Function Function I/O I/O WD, I/O I/O I/O WD, I/O SDI, I/O SDI, I/O SDI, I/O I/O I/O I/O GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND ...
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... I/O I/O 95 I/O I/O 96 I/O I/O 97 I/O I CCA CCA 99 GND GND 100 NC I/O 101 I/O I/O 102 I/O I/O 103 NC I/O 104 I/O I/O 105 I/O I/O A42MX24 A42MX09 Function Pin Number Function I/O 106 I/O 107 I/O 108 I/O 109 I/O 110 I/O 111 I/O 112 I/O 113 I/O 114 GND 115 I/O 116 SDO, TDO, I/O 117 WD, I/O 118 WD, I/O 119 I/O 120 V 121 CCI I/O 122 WD, I/O ...
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... Function 141 NC I/O 142 I/O I/O 143 I/O I/O 144 I/O I/O 145 GND GND 146 NC I/O 147 I/O I/O 148 I/O I/O 149 I/O I/O 150 NC V CCA A42MX24 A42MX09 Function Pin Number Function I/O 151 I/O 152 I/O 153 I/O 154 GND 155 I/O 156 I/O 157 I/O 158 I/O 159 MODE V 160 CCA v6.0 160-Pin PQFP A42MX16 A42MX24 Function Function NC I/O ...
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PQFP Package 208 1 Figure 2-6 • 208-Pin PQFP Package (Top View) 208-Pin PQFP v6.0 40MX and 42MX FPGA Families 2-13 ...
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FPGA Families 208-Pin PQFP A42MX16 A42MX24 Pin Number Function Function 1 GND GND CCA 3 MODE MODE 4 I/O I/O 5 I/O I/O 6 I/O I/O 7 I/O I/O 8 I/O I ...
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PQFP A42MX16 A42MX24 Pin Number Function Function 71 I/O WD, I/O 72 I/O I/O 73 I/O I/O 74 I/O I/O 75 I/O I/O 76 I/O I/O 77 I/O I/O 78 GND GND CCA CCA 80 NC ...
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FPGA Families 208-Pin PQFP A42MX16 A42MX24 Pin Number Function Function 141 NC I/O 142 I/O I/O 143 I/O I/O 144 I/O I/O 145 I/O I/O 146 NC I/O 147 NC I/O 148 NC I/O 149 NC I/O ...
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PQFP Package 240 1 • • • Figure 2-7 • 240-Pin PQFP Package (Top View) 40MX and 42MX FPGA Families 240-Pin PQFP v6.0 • • • 2-17 ...
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FPGA Families 240-Pin PQFP Pin A42MX36 Number Function Number 1 I/O 2 DCLK, I/O 3 I/O 4 I/O 5 I/O 6 WD, I/O 7 WD, I CCI 9 I/O 10 I/O 11 I/O 12 I/O ...
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PQFP 240-Pin PQFP Pin A42MX36 Pin Number Function Number 141 I/O 176 142 WD, I/O 177 143 WD, I/O 178 144 I/O 179 145 I/O 180 146 I/O 181 147 I/O 182 148 I/O 183 149 I/O 184 150 ...
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FPGA Families 80-Pin VQFP Figure 2-8 • 80-Pin VQFP 80-Pin VQFP v6.0 ...
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VQFP Pin A40MX02 A40MX04 Number Function Function 1 I I/O 5 I/O I/O 6 I/O I/O 7 GND GND 8 I/O I/O 9 I/O I/O 10 I/O I/O 11 I/O ...
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FPGA Families 100-Pin VQFP Package 100 1 Figure 2-9 • 100-Pin VQFP Package (Top View 100-Pin VQFP v6.0 ...
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... I/O I/O 59 I/O I/O 60 I/O I/O 61 I/O I CCA CCA CCI CCI CCA CCA 66 I/O I/O 67 I/O I/O 68 I/O I/O 69 I/O I/O 70 GND GND v6.0 40MX and 42MX FPGA Families 100-Pin VQFP Package Pin A42MX09 A42MX16 Number Function Function 71 I/O I/O 72 I/O I/O 73 I/O I/O 74 I/O I/O 75 I/O I/O 76 I/O I/O 77 SDI, I/O SDI, I/O 78 I/O I/O 79 I/O I/O 80 I/O I/O 81 I/O I/O 82 GND GND 83 I/O I/O 84 I/O I/O 85 PRA, I/O ...
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FPGA Families 176-Pin TQFP Package 176 1 Figure 2-10 • 176-Pin TQFP Package (Top View 176-Pin TQFP v6.0 ...
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... I/O 21 I/O I I/O 23 GND GND CCI CCA CCA CCI CCA 29 NC I/O 30 I/O I/O 31 I/O I/O 32 I/O I I/O I/O 35 I/O I/O A42MX24 A42MX09 Function Pin Number Function GND 36 MODE 37 I/O 38 I/O 39 I/O 40 I/O 41 I/O 42 I/O 43 I/O 44 I/O 45 I CCA I/O 49 I/O 50 I/O 51 I/O 52 GND 53 I/O 54 I/O 55 I/O 56 I/O 57 GND ...
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... I/O 126 I/O 127 I/O 128 I/O 129 I/O 130 I/O 131 I/O 132 I/O 133 I/O 134 I/O 135 I/O 136 I/O 137 I/O 138 I/O 139 I/O 140 v6.0 176-Pin TQFP A42MX09 A42MX16 A42MX24 Function Function Function GND GND GND NC I/O I/O NC I/O TCK, I CCA CCA CCA GND GND GND CCI CCI CCI ...
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... I/O I/O 151 NC I/O 152 PRA, I/O PRA, I/O 153 I/O I/O 154 CLKA, I/O CLKA, I/O 155 V V CCA CCA 156 GND GND 157 I/O I/O 158 CLKB, I/O CLKB, I/O A42MX24 A42MX09 Function Pin Number Function I/O 159 I/O 160 PRB, I/O I/O 161 WD, I/O 162 WD, I/O 163 I/O 164 I/O 165 I/O 166 I/O 167 WD, I/O 168 WD, I/O 169 PRA, I/O 170 I/O 171 ...
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FPGA Families 208-Pin CQFP ) 208207206205204203202201200 Pin #1 Index Figure 2-11 ...
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CQFP 208-Pin CQFP Pin A42MX36 Pin Number Function Number 1 GND CCA 3 MODE I/O ...
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FPGA Families 208-Pin CQFP Pin A42MX36 Number Function Number 141 I/O 142 I/O 143 I/O 144 I/O 145 I/O 146 I/O 147 I/O 148 I/O 149 I/O 150 GND 151 I/O 152 I/O 153 I/O 154 I/O ...
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CQFP 256255254253252251250249248 Pin #1 Index Figure 2-12 • 256-Pin CQFP (Top View) 40MX ...
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FPGA Families 256-Pin CQFP Pin A42MX36 Number Function Number GND 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 GND 11 I/O 12 I/O 13 I/O 14 I/O ...
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CQFP 256-Pin CQFP Pin A42MX36 Pin Number Function Number 141 I/O 176 142 I/O 177 143 I/O 178 144 I/O 179 145 I/O 180 146 I/O 181 147 I/O 182 148 I/O 183 149 I/O 184 150 I/O 185 ...
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FPGA Families 272-Pin BGA Package Figure 2-13 • 272-Pin BGA Package (Top View ...
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PBGA 272-Pin PBGA Pin A42MX36 Pin Number Function Number A1 GND B16 A2 GND B17 A3 I/O B18 A4 WD, I/O B19 A5 I/O B20 A6 I WD, I WD, I I/O C4 ...
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FPGA Families 272-Pin PBGA Pin A42MX36 Number Function Number L9 GND L10 GND L11 GND L12 GND L17 V CCI L18 I/O L19 I/O L20 TCK, I/O M1 I/O M2 I CCI M9 ...
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Datasheet Information List of Changes The following table lists critical changes that were made in the current version of the document. Previous version Changes in current version ( v5.1 The "Ease of Integration" section The "Temperature Grade ...
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... Note that the “Package Characteristics and Mechanical Drawings” section has been eliminated from the data sheet. The mechanical drawings are now contained in a separate document, “Package Characteristics and Mechanical Drawings,” available on the Actel web site. Datasheet Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as " ...
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... Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. Actel Corporation Actel Europe Ltd. 2061 Stierlin Court Dunlop House, Riverside Way Mountain View, CA Camberley, Surrey GU15 3YL 94043-4655 USA United Kingdom Phone 650.318.4200 Phone +44 (0)1276 ...