IP101 IC Plus Corp., IP101 Datasheet
IP101
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IP101 Summary of contents
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... IP101 Transceiver is fabricated with advanced CMOS technology, which the chip only requires 3.3V as power supply and consumes very low power in the Auto Power Saving mode. IP101 can be implemented as Network Interface Adapter with RJ-45 for twisted-pair connection or MAU for Fiber Connection. implemented into HUB, Switch, Router, Access Point ...
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... IP101-DS-R01 Initial release. IP101-DS-R02 IP101-DS-R03 Remove RMII, SNI function. Add digital loopback requirement. IP101-DS-R04 Add reset timing description to Pin 42 RESET_N in page 9 Confidential. Copyright © 2003, IC Plus Corp. Preliminary Data Sheet Change Description 2/32 IP101 Sep. 15, 2003 IP101-DS-R04 ...
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... Negotiation 100Mbps Recovery 10Mbps 100Mbps Parallel to Serial MLT3/NRZI Decoder 10Mbps 100Mbps NRZ/ Manchester DSP Engine Encoder 10Mbps 100Mbps RJ-45 Connector Figure 1: Flow chart of IP101 3/32 IP101 Preliminary Data Sheet RXD 10Mbps 4B/5B Serial to Parallel 10Mbps Machester/ NRZ Decoder 5B Parallel 10Mbps Clock Recovery Clock 10Mbps ...
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... RESET_N 43. ISOL Fast Ethernet Single Phy Transceiver Chip 44. NC 45. DGND 46. X1 47. X2 48. INTR/ FIB_DIS Confidential. Copyright © 2003, IC Plus Corp. IP101 48 pins LQFP package Figure 2 : IP101 pins assignment 4/32 IP101 Preliminary Data Sheet 24. RX_ER /FIBMOD 23. CRS /LEDMOD 22. RX_DV 21. RXD0 20. RXD1 19. RXD2 18. RXD3 17 ...
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... RX_DV pin uses this pin as its reference under MII. O Receive Data: These 4 data lines are transmission path for PHY to send data to MAC and they are synchronizing with RX_CLK. 5/32 IP101 Preliminary Data Sheet Description Internal Pull-Down Internal Pull-Up Power Open Drain Description Sep. 15, 2003 IP101-DS-R04 ...
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... LEDMOD: During power on reset, this pin status is latched to determine at which LED mode to operate, please refer to the LED pins description. (Notice: This pin is pulled down internally) 6/32 IP101 Preliminary Data Sheet Description Sep. 15, 2003 IP101-DS-R04 ...
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... This pin can be directly connected to GND or VCC. (An internal weak pulled-up is used to enable N-WAY as a default) I Set high to put the IP101 into APS mode. This pin can be directly (PU) connected to GND or VCC. Refer to Section 7 for more information. (An internal weak pulled-up is used to enable APS ...
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... LED. The driving polarity, active low or active high, is determined by each latched status of the PHY address [4:0] during power-up reset. If latched status is high then it will be active low, and if latched status is Low then it will be active high. Moreover, IP101 provides 2 LED nd operation modes ...
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... FIB_DIS: For some applications in TP mode, fiber mode will be selected by pin24 during initialization although TP mode is the desired application. IP101 provides the other option. If pin48 has been pulled low by resistor during initialization, fiber mode would be disabled even pin24 has been pulled high during initialization. ...
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... PHY to default state. This bit is self-clearing Software reset 0 = Normal operation 14 Loop-back This bit enables loop-back of transmit data to the receive data path, i.e., TXD to RXD. IP101 requires at least 512us to link after programming this bit. TX/RX packets should be activated after 512us enable loop-back 0 = normal operation 13 Speed Selection This bit sets the speed of transmission ...
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... Reserved 6 MF Preamble The IP101 will accept management frames with preamble Suppression suppressed. The IP101 accepts management frames without preamble. A Minimum of 32 preamble bits are required for the first SMI read/write transaction after reset. One idle bit is required between any two management transactions as per IEEE802 ...
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... Register Descriptions (continued) Bit Name Register 2 : PHY Identifier Register 1 15:0 PHYID1 PHY identifier ID for software recognize IP101 Bit Name Register 3 : PHY Identifier Register 2 15:0 PHYID2 PHY identifier ID for software recognize Note : Register 2 and register 3 identifier registers altogether consist of Vender model, model revision number and Organizationally Unique identifier (OUI) information. Total of 32 bits allocate in these 2 registers and they can return all zeroes in all bits if desired. Register 2 contains OUI’ ...
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... Register Descriptions (continued) Register 4 lists the advertised abilities during auto-negotiation for what will be transmitted to IP101’s Link Partner. Bit Name Register 4 : Auto-Negotiation Advertisement Register 15 NP Next Page bit transmitting the primary capability data page 1 = transmitting the protocol specific data page 14 Reserved ...
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... Selector Binary encoded selector supported by this node. Currently only CSMA/CD <00001> is specified. No other protocols are supported. Confidential. Copyright © 2003, IC Plus Corp. Preliminary Data Sheet Description/Usage 14/32 IP101 Default value (h): 0001 1, RW <00001>, RO Sep. 15, 2003 IP101-DS-R04 ...
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... Link Partner’s binary encoded node selector Currently only CSMA/CD <00001> is specified Confidential. Copyright © 2003, IC Plus Corp. Preliminary Data Sheet Description/Usage 15/32 IP101 Default value (h): 0080 <00000>, RO Sep. 15, 2003 IP101-DS-R04 ...
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... LP_NW_ABLE 1 = link partner supports Nway auto-negotiation. Confidential. Copyright © 2003, IC Plus Corp. Description/Usage It is cleared automatically 16/32 IP101 Preliminary Data Sheet Default value (h): 0000 after the 0, RO Sep. 15, 2003 IP101-DS-R04 ...
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... Name Register 16 : PHY Spec. Control Register 15 Debug Mode 0 = IP101 operates at normal mode 1 = IP101 operates at debug mode, for internal use only (Notice the functionalities of bit 16:<14>, 16:<13>, 16:<12>, and 16:<4:0> depend on the setting of this bit 16:<15> Software reset(reg0.15) will not set this bit to default value if this bit has been programmed to “1”. Hardware reset or power on reset will set it to default value ...
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... Name Register 16 : PHY Spec. Control Register (continued) 2 Repeater Mode Set high to put IP101 into repeater mode Software reset(reg0.15) will not set this bit to default value if this bit has been programmed to “1”. Hardware reset or power on reset will set it to default value. ...
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... Speed Change Flag to indicate speed change interrupt 0 Duplex Change Flag to indicate duplex change interrupt Confidential. Copyright © 2003, IC Plus Corp. Preliminary Data Sheet Description/Usage 19/32 IP101 Default value (h): 0E00 0, R R/W 1, R/W 1, R/W 1, R Sep. 15, 2003 IP101-DS-R04 ...
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... Functional Description IP101 10/100Mbps Ethernet PHY Transceiver integrates 100 Base-TX, 100 Base-FX and 10 Base-T modules into a single chip. IP101 acts as an interface between physical signaling and Media Access Controller (MAC). IP101 has several major functions: 1. PCS layer (Physical Coding Sub-Layer): This function contains transmit, receive and carrier sense functional circuitries ...
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... The extracted data is parallelized into 5-bits wide data, which are then Confidential. Copyright © 2003, IC Plus Corp. D/A & line driver Manchester/NRZ Decoder NRZI/MLT-3 Encoder D/A & line driver Descrambler 4B/5B Decoder D/A & line driver Serial to Parallel 4B/5B Decoder 21/32 IP101 Preliminary Data Sheet TXO Serial to Parallel RXD TXO RXD TXO RXD Sep. 15, 2003 IP101-DS-R04 ...
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... Register 4. Pin 37 (AN_ENA), 38 (DLPX), 39 (SPD) can be configured manually to set IP101’s transmission ability. 1. Enabling Pin 37 (set high) will put IP101 to N-Way mode, if set low to pin 37, it will put IP101 into forced mode. 2. Pin 38 will configure Duplex ability of IP101, at high, IP101 is set to Full-Duplex and low will let IP101 enter half duplex mode ...
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... H Auto MDIX function Since Auto MDIX function is part of AN function, IP101 supports Auto MDIX function only enabled. IP101 will keep sensing incoming signal in MDI RX pair incoming signal is detected, IP101 will switch TX and RX pairs automatically trying to establish connection disabled by setting Pin37=0 during reset, Auto-MDIX will be disabled automatically ...
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... APS mode in bit 1 of Register 16: Set high to this bit will let PHY into power saving mode, MDC and MDIO are also activated. Analog off in bit 0 of Register 16: Enable this bit will put IP101 in analog off state. This will power down all analog functions but internal 25MHz operating clock is active, and MDC and MDIO are also activated. ...
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... Twisted Pair recommendation When routing the TD+/- signal traces from IP101 to transformer, the traces should be as short as possible, the termination resistors should be as close as possible to the output of the TD+/- pair of IP101. Center tap of primary winding of these transformers must be connected to analog 2.5V respectively recommended that RD+/- trace pair be route such that the space between it and others is three times space, which can separate individual traces from one another ...
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... Circuit Diagram There are 2 suggested circuit diagrams for IP101. 5.1 MII interface with UTP R1 Chip Diagram VDD33 5.1K MDC MDIO TXD0 TXD1 TXD2 TXD3 R3 TX_EN VDD33 CRS/LEDMOD TX_CLK 5.1K RX_DV RXD0 To set the LED RXD1 mode 2 on RXD2 RXD3 RX_CLK COL CRS/LEDMOD RX_ER/FIBMOD Y1 PHYAD0/LED0 ...
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... VDD or GND directly. Title Size Document Number A Date: Tuesday, June 24, 2003 27/32 IP101 Preliminary Data Sheet VCC5V C22 10U VDD33 C24 10U Analog and Digital 3.3V connection L2 VDD33 AVDD33 BEAD C16 0.1U IP101 Chip Circuit Diagram Rev MII UTP <RevCode> Sheet Sep. 15, 2003 IP101-DS-R04 ...
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... Tuesday, June 24, 2003 Sheet 0.01U/25V C3 470u/25V 9 GND 8 TD+ 7 TD- 6 VCC 5 VCC 4 SD+ 3 RD- 2 RD+ 1 GND Agilent 5103T C9 0.01U/25V IP101 Chip Circuit Diagram Document Number Rev MII Fiber Tuesday, June 24, 2003 Sheet Sep. 15, 2003 IP101-DS-R04 Rev <RevCode> <RevCode> ...
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... This configuration shows Enable: Auto negotiation, Full duplex, 100Mbps, Link Down Power Saving, MII interface Disable: Isolate, Repeater mode 2. These senven configuration pins could be connected to VDD or GND directly. Title IP101 Chip Circuit Diagram Size Document Number A Date: Tuesday, June 24, 2003 29/32 IP101 ...
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... Vout=Vcc or GND Vin=Vcc or GND Iout=0mA 30/32 IP101 Preliminary Data Sheet Typical Maximum 3.3V 3.6V 125°C Typical Maximum 3.3V 3.6V 70°C Min Max 0.5*Vcc Vcc+0.5V -0.5V 0.3*Vcc 0.9*Vcc Vcc 0.1*Vcc 200mA Vdd-1.16V Vdd-0.88V Vdd-1.81V Vdd-1.47V Vdd-1.02V Vdd-1.62V Sep. 15, 2003 IP101-DS-R04 ...
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... Order Information Part No. IP101 48-PIN LQFP Confidential. Copyright © 2003, IC Plus Corp. Package Notice - 31/32 IP101 Preliminary Data Sheet Sep. 15, 2003 IP101-DS-R04 ...
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... FAX : 886-2-2696-2220 Sep. 15, 2003 IP101-DS-R04 ...