EM635327Q-10 Etron Technology, Inc., EM635327Q-10 Datasheet
EM635327Q-10
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EM635327Q-10 Summary of contents
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... AC1 t Access time from CLK(max.) AC3 t Row Cycle time(min.) RC Ordering Information Part Number Frequency EM635327Q-12 83MHz EM635327R-12 83MHz EM635327TQ-12 83MHz EM636327TR-12 83MHz EM635327Q-10 100MHz EM635327R-10 100MHz EM635327TQ-10 100MHz EM635327TR-10 100MHz EM635327Q-9 110MHz EM635327R-9 110MHz EM635327TQ-9 110MHz EM635327TR-9 110MHz EM635327Q-8 125MHz EM635327R-8 ...
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Block Diagram CLK CLOCK BUFFER CKE CS# RAS# COMMAND CAS# DECODER WE# DSF COLUMN COUNTER A 8 ADDRESS A 0 BUFFER REFRESH COUNTER Pin Assignment (Top View) Forward Type DQ3 DDQ DQ4 3 DQ5 ...
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Pin Descriptions Table 1 shows the details for pin number, symbol, type, and description. Pin Number Symbol Type Description 55 CLK Input Clock: CLK is driven by the system clock. All SGRAM input signals are sampled on the positive edge ...
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DSF Input Define Special Function: The DSF signal defines the operation commands in conjunction with the RAS# and CAS# and WE# signals and is latched at the positive edges of CLK. The DSF input is used to select the ...
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Operation Mode Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 2 shows the truth table for the operation commands. Command BankActivate & Masked Write Disable BankActivate & Masked Write Enable BankPrecharge PrechargeAll ...
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Commands 1 BankActivate & Masked Write Disable command (RAS# = "L", CAS# = "H", WE# = "H", DSF = "L" Bank, A0-A8 = Row Address) The BankActivate command activates the idle bank designated by the BS (Bank Select) ...
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The DQs go into high-impedance at the end of the burst unless other command is initiated. The burst length, burst sequence, and CAS# latency ...
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CLK DQM COM MAND NOP READ A DQ's : "H" or "L" Read to Write Interval CLK DQM COM MAND NOP NOP CAS# latency=1 t CK1 , DQ's CAS# latency=2 t CK2 , DQ's ...
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CLK Bank, ADDRESS Col A COM M AND READ A NO CAS# latency=1 DOUT CK1 , DQ's CAS# latency=2 t CK2 , DQ's CAS# latency=3 t CK3 , DQ's Read to Precharge 6 Read ...
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DSF BankActivate command MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0 Note: Only the lower byte is shown. The operation is identical for other bytes. Write Per Bit (I/O Mask) Block Diagram A write burst without auto ...
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Once the Read command is registered, the data inputs will be ignored and writes will not be executed CLK COM MAND NOP WRITE A CAS# ...
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Block Write command is used to mask specific column/byte combinations within the block. The mapping of the DQ inputs to the column/byte combinations is shown in following table. The overall Block Write mask consists of a ...
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DQ Column Address DQ Planes Inputs A2 A1 DQ0 0 0 DQ1 0 0 DQ2 0 1 DQ3 0 1 DQ4 1 0 DQ5 1 0 DQ6 1 1 DQ7 1 1 DQ8 0 0 DQ9 0 0 DQ10 0 ...
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Block Write and AutoPrecharge command (RAS# = "H", CAS# = "L", WE# = "H", DSF = "H" Bank "H", A3-A7 = Column Address, DQ0-DQ31 = Column Mask) The Block Write and AutoPrecharge command performs the ...
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The mode register is divided into various fields depending on functionality. Burst Length Field (A2~A0) This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length ...
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This field specifies the number of clock cycles from the assertion of the Read command to the first read data. The minimum whole value of CAS# Latency depends on the frequency of CLK. The minimum whole value satisfying the following ...
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CAS# = "H", WE# = "L", DSF = "L") The Burst Stop command is used to terminate either fixed-length or full-page bursts. This command is only effective in a read/write burst without the auto precharge function. The ...
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CAS# = "L", WE# = "H", DSF = "L", CKE = "L", BS, A0-A8 = Don't care) The SelfRefresh is another refresh mode available in the SGRAM the preferred refresh mode for data retention and ...
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Absolute Maximum Rating Symbol Input, Output Voltage IN OUT Power Supply Voltage DD DDQ T Operating Temperature OPR T Storage Temperature STG T Soldering Temperature (10s) SOLDER P Power Dissipation D I Short Circuit ...
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Recommended D.C. Operating Conditions (V Description/Test condition Operating Current ¡Ù (min), Outputs Open Address changed once during CK Burst Length = 1 Precharge Standby Current in non-power down mode (min), CS# ¡Ù CKE ...
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Electrical Characteristics and Recommended A.C. Operating Conditions (V = 3.3V¡Ó0.3V 0~70¢J ) (Note Symbol A.C. Parameter t Row cycle time RC (same bank) t RAS# to CAS# delay RCD (same bank) t Precharge ...
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Note: 1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. 2. All voltages are referenced These parameters depend on the cycle rate and these values are measured by the ...
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Latency relationship to frequency (Unit: clock cycles) -8 Version (Calculation with t CK Clock period 72ns CK 24ns 3 12ns 6 8ns 9 -10 Version (Calculation with t CK Clock period 90ns ...
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Timing Waveforms Figure 1. AC Parameters for Write Timing CLK CK2 CKE CS# RAS WE# DSF ...
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Figure 2. AC Parameters for Read Timing CLK t t CK2 CKE CS WE# DSF RAx ...
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Figure 3. Auto Refresh (CBR CLK t CK2 CKE CS# RAS WE# DSF A0~ DQM DQ PrechargeAll AutoRefresh Command Command Preliminary (Burst Length=4, CAS# Latency=2) T6 ...
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Figure 4. Power on Sequene and Auto Refresh (CBR CLK t CK2 High level CKE is reauired CS# RAS# CAS# WE# DSF Address Key A0-A7 DQM Hi-Z ...
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Figure 5. Self Refresh Entry & Exit Cycle Clock *Note 2 *Note 1 CKE t IS CS# RAS# *Note DSF DQM Hi-Z DQ Self Refresh ...
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Figure 6.1. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency= CLK t CK1 CKE CS# RAS WE# DSF RAx A0- A7 RAx CAx DQM Hi-Z DQ ...
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Figure 6.2. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency= CLK t CK2 CKE CS# RAS WE# DSF RAx A0 -A7 CAx RAx DQM Hi-Z DQ ...
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Figure 6.3. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency= CLK t CK3 CKE CS# RAS WE# DSF RAx A0 -A7 RAx CAx DQM Hi-Z ...
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Figure 7.1. Clock Suspension During Burst Write (Using CKE) (Burst Length = 4, CAS# Latency = CLK t CK1 CKE CS# RAS WE# DSF RAx A0- A7 RAx ...
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Figure 7.2. Clock Suspension During Burst Write (Using CKE) (Burst Length=4, CAS# Latency= CLK t CK2 CKE CS# RAS WE# DSF RAx A0 -A7 RAx CAx DQM Hi-Z DQ ...
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Figure 7.3. Clock Suspension During Burst Write (Using CKE) (Burst Length=4, CAS# Latency= CLK t CK3 CKE CS# RAS WE# DSF RAx A0- A7 RAx CAx DQM DQ Hi-Z ...
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Figure 8. Power Down Mode and Clock Mask CLK t CK2 t IS CKE CS# RAS WE# BS RAx A 8 RAx A0~A7 DQM Hi-Z DQ ACTIVE STANDBY Activate Command Bank A ...
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Figure 9.1. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency= CLK t CK1 CKE CS# RAS WE# DSF RAw RAw CAw A0~ Hi-Z DQ ...
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Figure 9.2. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency= CLK t CK2 CKE CS# RAS WE# DSF RAw CAw RAw A0~ Hi-Z DQ ...
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Figure 9.3. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency= CLK t CK3 CKE CS# RAS WE# DSF RAw RAw CAw A0~ Hi-Z DQ ...
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Figure 10.1. Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency= CLK t CK1 CKE CS# RAS WE# DSF RBw RBw CBw A0~ Hi-Z DQ ...
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Figure 10.2. Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency= CLK t CK2 CKE CS# RAS WE# DSF RBw A0~A7 CBw RBw DQ M Hi-Z DQ ...
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Figure 10.3. Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency= CLK t CK3 CKE CS# RAS WE# DSF RBw CBw A0~A7 RBw DQ M Hi-Z DQ ...
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Figure 11.1. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency= CLK t CK1 CKE High CS# RAS WE# DSF RBx RBx A0~A7 CBx t RCD t AC1 DQ ...
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Figure 11.2. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency= CLK t CK2 High CKE CS# RAS WE# DSF RBx RBx CBx A0~ RCD AC2 DQ ...
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Figure 11.3. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency= CLK t CK3 High CKE CS# RAS WE# DSF RBx CBx RBx A0~ RCD AC3 DQ ...
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Figure 12.1. Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency= CLK t CK1 High CKE CS# RAS WE# DSF RAx A0~A7 RAx CAx t RCD DQ M Hi-Z ...
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Figure 12.2. Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency= CLK t CK2 High CKE CS# RAS WE# DSF RAx A0~A7 RAx CAx t RCD DQ M Hi-Z ...
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Figure 12.3. Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency= CLK t CK3 High CKE CS# RAS WE# DSF RAx RAx CAx A0~A7 t RCD DQ M Hi-Z ...
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Figure 13.1. Read and Write Cycle CLK t CK1 CKE CS# RAS WE# DSF RAx RAx CAx A0~ Hi-Z DQ Ax0 Ax1 Ax2 Activate Command Bank A ...
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Figure 13.2. Read and Write Cycle CLK t CK2 CKE CS# RAS WE# DSF RAx RAx CAx A0~ Hi-Z DQ Ax0 Activate Read Command Command Bank A ...
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Figure 13.3. Read and Write Cycle CLK t CK3 CKE CS# RAS WE# DSF RAx RAx CAx A0~ Hi-Z DQ Read Activate Command Command Bank A Bank ...
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Figure 14.1. Interleaving Column Read Cycle CLK t CK1 CKE CS# RAS WE# DSF RAx RBw RAx RAx RBw A0~ RCD AC1 DQM Hi-Z DQ Ax0 ...
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Figure 14.2. Interleaving Column Read Cycle CLK t CK2 CKE CS# RAS WE# DSF RAx RAx RAx CAy RAx A0~ RCD AC2 DQ M Hi-Z DQ Ax0 ...
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Figure 14.3. Interleaved Column Read Cycle CLK t CK3 CKE CS# RAS WE# DSF RAx RBx RAx CAx RBx A0~A7 t RCD DQ M Hi-Z DQ Activate Read Command ...
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Figure 15.1. Interleaved Column Write Cycle CLK t CK1 CKE CS# RAS WE# DSF RAx RBw RAx CAx RBw A0~A7 t RCD DQM t RRD Hi-Z DQ DAx0 ...
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Figure 15.2. Interleaved Column Write Cycle CLK t CK2 CKE CS WE# DSF RAx RBw RAx CAx RBw A0~A7 t RCD DQM t RRD Hi-Z DQ ...
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Figure 15.3. Interleaved Column Write Cycle CLK t CK3 CKE CS# RAS WE# DSF RAx RBw RAx CAx RBw A0~A7 t RCD > t RRD RRD(min) ...
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Figure 16.1. Auto Precharge after Read Burst CLK t CK1 High CKE CS# RAS WE# DSF RAx RBx RAx CAx RBx CBx A0~ Hi-Z DQ Ax1 Ax2 ...
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Figure 16.2. Auto Precharge after Read Burst CLK t CK2 High CKE CS# RAS DSF WE RAx RBx RAx RBx CAx A0~A7 DQM Hi-Z DQ Ax1 Ax0 Activate Read ...
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Figure 16.3. Auto Precharge after Read Burst CLK t CK3 High CKE CS# RAS WE# DSF RAx RBx CAx A0~A7 RAx RBx DQ M Hi-Z DQ Activate Activate Command ...
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Figure 17.1. Auto Precharge after Write Burst CLK t CK1 High CKE CS# RAS WE# DSF RAx RBx RAx CAx RBx CBx A0~ Hi-Z DQ DAx0 DAx1 ...
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Figure 17.2. Auto Precharge after Write Burst CLK t CK2 High CKE CS# RAS WE# DSF RAx RBx RAx CAx RBx A0~ Hi-Z DQ DAx0 DAx1 DAx2 ...
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Figure 17.3. Auto Precharge after Write Burst CLK t CK3 High CKE CS# RAS WE# DSF RAx RBx CAx A0~A7 RAx RBx DQM Hi-Z DQ DAx0 DAx1 DAx2 ...
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Figure 18.1. Full Page Read Cycle CLK t CK1 High CKE CS# RAS WE# DSF RAx RBx RAx CAx RBx A0~A7 t RRD DQ M Hi-Z DQ Ax+1 Ax+2 ...
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Figure 18.2. Full Page Read Cycle CLK t CK2 High CKE CS# RAS WE# DSF RAx RBx RAx CAx RBx A0~A7 DQM Hi Ax+1 Ax+2 Ax-2 ...
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Figure 18.3. Full Page Read Cycle CLK t CK3 High CKE CS# RAS WE# DSF RAx RBx RAx CAx RBx A0~ Hi-Z DQ Activate Read Activate Command ...
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Figure 19.1. Full Page Write Cycle CLK t CK1 High CKE CS# RAS WE# DSF RAx RBx CAx RBx RAx A0~ Hi-Z DQ DAx DAx+ 1 DAx+ ...
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Figure 19.2. Full Page Write Cycle CLK t CK2 High CKE CS# RAS WE# DSF RAx RBx RAx CAx A0~A7 RBx DQ M Hi-Z DQ DAx DAx+ 1 DAx+ ...
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Figure 19.3. Full Page Write Cycle CLK t CK3 High CKE CS# RAS WE# DSF RAx RBx RAx CAx RBx A0~ Hi-Z DQ DAx DAx+ 1 DAx+ ...
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Figure 20. Byte Write Operation CLK t CK2 High CKE C S# RAS DSF RAx A0 ~A7 CAx RAx DQM0 DQM1~3 DQ0 - DQ7 DQ8 - DQ31 ...
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Figure 21. Burst Read and Single Write Operation CLK t CK2 High CKE CS# RAS WE# DSF RAx RAx CAx A0~A7 DQM0 DQM1~3 Hi-Z DQ0 - DQ7 Ax0 Hi-Z DQ8 ...
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Figure 22. Full Page Burst Read and Single Write Operation (Burst Length=Full Page, CAS# Latency= CLK t CK3 High CKE CS# RAS WE# DSF RAv RAv CAv A0~A7 DQM0 DQM1~3 ...
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Figure 23. Random Row Read (Interleaving Banks) (Burst Length=2, CAS# Latency= CLK t CK1 High CKE Begin Auto Begin Auto Precharge Precharge Bank B Bank A CS# RAS WE# DSF BS A ...
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Figure 24. Full Page Random Column Read CLK t CK2 CKE CS# RAS WE# DSF RAx RBx RAx RBx CAx CBx A0~A7 DQM t t RRD RCD DQ Activate ...
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Figure 25. Full Page Random Column Write CLK t CK2 CKE CS# RAS WE# DSF RAx RBx RAx RBx CAx A0~A7 CBx RRD RCD DQ ...
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Figure 26.1. Precharge Termination of a Burst CLK t CK1 CKE CS# RAS WE# DSF RAx RAx CAx A0~ DAx0 DAx1 DAx2 DAx3 DAx4 Activate Precharge ...
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Figure 26.2. Precharge Termination of a Burst (Burst Length=8 or Full Page, CAS# Latency= CLK t CK2 High CKE CS# RAS WE# DSF RAx RAx CAx A0~ ...
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Figure 26.3. Precharge Termination of a Burst (Burst Length= Full Page, CAS# Latency= CLK t CK3 High CKE CS# RAS WE# DSF RAx RAx CAx A0~A7 t ...
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EtronTech 100 Pin 14x20 mm TQFP & QFP Package Outline Drawing Information PIN #1 L (L1) SECTION Symbol Definition A Overall Height A1 Stand Off A2 Body Thickness b Lead Width C Lead Thickness ...