21150AB Intel Corporation, 21150AB Datasheet
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21150AB
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21150AB Summary of contents
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PCI-to-PCI Bridge Product Features Complies fully with the PCI Local Bus Specification, Revision 2.1 Complies fully with the Advanced Configuration Power Interface (ACPI) Specification Complies fully with the PCI Power Management Specification, Revision 1.0 Complies fully with Revision 1.0 ...
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... Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel’s website at http://www.intel.com. Copyright © Intel Corporation, 1998 *Third-party brands and names are the property of their respective owners. ...
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Contents 1.0 Introduction......................................................................................................................... 1 1.1 Architecture ........................................................................................................... 3 1.2 Data Path .............................................................................................................. 5 1.3 Posted Write Queue .............................................................................................. 6 1.4 Delayed Transaction Queue.................................................................................. 6 1.5 Read Data Queue ................................................................................................. 6 2.0 Signal Pins ......................................................................................................................... 7 2.1 Primary PCI Bus Interface ...
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Transaction Termination ..................................................................................... 47 4.8.1 Master Termination Initiated by the 21150 ............................................. 47 4.8.2 Master Abort Received by the 21150 ..................................................... 48 4.8.3 Target Termination Received by the 21150 ........................................... 50 4.8.3.1 Delayed Write Target Termination Response ........................... ...
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Bus Parking ............................................................................................87 10.0 General-Purpose I/O Interface .........................................................................................89 10.1 gpio Control Registers.........................................................................................89 10.2 Secondary Clock Control.....................................................................................90 10.3 Live Insertion .......................................................................................................92 11.0 Clocks...............................................................................................................................95 11.1 Primary and Secondary Clock Inputs ..................................................................95 11.2 Secondary Clock Outputs....................................................................................95 11.3 Disabling Unused Secondary Clock Outputs ...
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Subsystem Vendor ID Register—Offset 34h........................................ 118 15.1.28 ECP Pointer Register—Offset 34h ....................................................... 118 15.1.29 Subsystem ID Register—Offset 36h .................................................... 119 15.1.30 Interrupt Pin Register—Offset 3Dh....................................................... 119 15.1.31 Bridge Control Register—Offset 3Eh ................................................... 119 15.1.32 Capability ID Register—Offset DCh ...
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Figures 1 21150 on the System Board.................................................................................. 2 2 21150 with Option Cards....................................................................................... 3 3 21150 on the System Board.................................................................................. 4 4 21150 Downstream Data Path .............................................................................. 5 5 21150 Pin Assignment ........................................................................................19 6 Flow-Through Posted Memory Write Transaction...............................................31 7 ...
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Device Number to IDSEL s_ad Pin Mapping ...................................................... 45 21 21150 Response to Delayed Write Target Termination ...................................... 50 22 21150 Response to Posted Write Target Termination ........................................ 51 23 21150 Response to Delayed Read Target Termination ...................................... ...
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Introduction The 21150 is a second-generation PCI-to-PCI bridge and is fully compliant with PCI Local Bus Specification, Revision 2.1. The 21150 provides full support for delayed transactions, which enables the buffering of memory read, I/O, and configuration transactions. The ...
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Figure 1. 21150 on the System Board Memory and Cache SCSI 2 CPU 21150 Core Graphics Logic PCI Bus 21150 ISA or LAN EISA ISA or EISA Bus Bridge Support PCI Option Slots PCI Bus PCI Option Slots ...
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Figure 2. 21150 with Option Cards 21150 Note: 1.1 Architecture The 21150 internal architecture consists of the following major functions: • PCI interface control logic for the primary and secondary PCI interfaces • Data path and data path control logic ...
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Figure 3. 21150 on the System Board Secondary Arbiter Clocks and Reset Primary Request and Grant Table 1. 21150 Functional Blocks (Sheet Function Blocks Primary and Secondary Control Primary-to-Secondary Data Path 4 Secondary Data Secondary ...
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Table 1. 21150 Functional Blocks (Sheet Secondary-to-Primary Data Path Configuration Registers Secondary Bus Arbiter Control 1.2 Data Path The data path consists of a primary-to-secondary data path for transactions and data flowing in the downstream direction and ...
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Posted Write Queue The posted write queue contains the address and data of memory write transactions targeted for the opposite interface. The posted write transaction can consist of an arbitrary number of data phases, subject to the amount ...
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Signal Pins This chapter provides detailed descriptions of the 21150 signal pins, grouped by function. Table 2 describes the signal pin functional groups, and the following sections describe the signals in each group. Table 2. Signal Pins Function Primary ...
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Primary PCI Bus Interface Signals Table 4 describes the primary PCI bus interface signals. Table 4. Primary PCI Bus Interface Signals (Sheet Signal Name p_ad<31:0> p_cbe_l<3:0> p_par p_frame_l p_irdy_l 8 Type Description Primary PCI interface ...
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Table 4. Primary PCI Bus Interface Signals (Sheet Signal Name p_trdy_l p_devsel_l p_stop_l p_lock_l p_idsel Preliminary Datasheet Type Description Primary PCI interface TRDY#. Signal p_trdy_l is driven by the target of a transaction to indicate the target’s ...
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Table 4. Primary PCI Bus Interface Signals (Sheet Signal Name p_perr_l p_serr_l p_req_l p_gnt_l 10 Type Description Primary PCI interface PERR#. Signal p_perr_l is asserted when a data parity error is detected for data received on ...
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Secondary PCI Bus Interface Signals Table 5 describes the secondary PCI bus interface signals. Table 5. Secondary PCI Bus Interface Signals (Sheet Signal Name s_ad<31:0> s_cbe_l<3:0> s_par s_frame_l Preliminary Datasheet Type Description Secondary PCI interface address/data. ...
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Table 5. Secondary PCI Bus Interface Signals (Sheet Signal Name s_irdy_l s_trdy_l s_devsel_l s_stop_l 12 Type Description Secondary PCI interface IRDY#. Signal s_irdy_l is driven by the initiator of a transaction to indicate the initiator’s ability ...
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Table 5. Secondary PCI Bus Interface Signals (Sheet Signal Name s_lock_l s_perr_l s_serr_l 2.3 Secondary Bus Arbitration Signals Table 6 describes the secondary bus arbitration signals. Table 6. Secondary PCI Bus Interface Signals (Sheet ...
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Table 6. Secondary PCI Bus Interface Signals (Sheet s_cfn_l 2.4 General-Purpose I/O Interface Signals Table 7 describes the general-purpose I/O interface signals. Table 7. General-Purpose I/O Interface Signals Signal Name gpio<3:0> 2.5 Clock Signals Table 8 ...
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Table 8. Clock Signals (Sheet s_clk s_clk_o<9:0> 2.6 Reset Signals Table 9 describes the reset signals. Table 9. Reset Signals Signal Name 1 bpcce p_rst_l s_rst_l 1. For 21150-AB and later revisions only Preliminary Datasheet Secondary interface ...
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Miscellaneous Signals Table 10 describes the miscellaneous signals. Table 10. Miscellaneous Signals Signal Name msk_in p_vio s_vio config66 p_m66ena s_m66ena 16 Type Description Secondary clock disable serial input. This input-only signal is used by the hardware mechanism to ...
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JTAG Signals Table 11 describes the JTAG signals. Table 11. JTAG Signals Signal Name tdi tdo tms tck trst_l Preliminary Datasheet Type Description JTAG serial data in. Signal tdi is the serial input through which JTAG instructions and test ...
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Pin Assignments This chapter describes the 21150 pins. It provides numeric and alphabetic lists of the pins and includes a diagram showing 21150 pin assignment. Figure 5 shows the 21150 pins. Figure 5. 21150 Pin Assignment vdd req_l<1> req_l<2> ...
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Numeric Pin Assignment Table 13 lists the 21150 pins in numeric order, showing the name, number, and signal type of each pin. Table 12 defines the signal type abbreviations. Table 12. Signal Types Signal Type ...
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Table 13. Numeric Pin Assignments (Sheet Pin vdd s_req_l<1> s_req_l<2> s_req_l<3> s_req_l<4> s_req_l<5> s_req_l<6> s_req_l<7> s_req_l<8> s_gnt_l<0> s_gnt_l<1> vss s_gnt_l<2> s_gnt_l<3> s_gnt_l<4> s_gnt_l<5> s_gnt_l<6> s_gnt_l<7> s_gnt_l<8> vss s_clk s_rst_l s_cfn_l gpio<3> gpio<2> vdd gpio<1> gpio<0> s_clk_o<0> s_clk_o<1> ...
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Table 13. Numeric Pin Assignments (Sheet Pin p_ad<19> p_ad<18> vdd p_ad<17> p_ad<16> vss p_cbe_l<2> p_frame_l vdd p_irdy_l p_trdy_l p_devsel_l p_stop_l vss p_lock_l p_perr_l p_serr_l p_par vdd p_cbe_l<1> p_ad<15> vss p_ad<14> p_ad<13> vdd p_ad<12> p_ad<11> vss p_ad<10> ...
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Table 13. Numeric Pin Assignments (Sheet Pin s_ad<7> vss s_cbe_l<0> s_ad<8> vdd s_ad<9> s_m66ena s_ad<10> vdd vss vdd vss s_ad<11> vss s_ad<12> s_ad<13> vdd s_ad<14> s_ad<15> vss s_cbe<1> s_par s_serr_l vdd s_perr_l s_lock_l s_stop_l vss s_devsel_l s_trdy_l ...
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Alphabetic Pin Assignment Table 14 lists the 21150 pins in alphabetic order, showing the name, number, and signal type of each pin. Table 12 defines the signal type abbreviations. Table 14. Alphabetic Pin Assignments. Pin 1 bpcce config66 ...
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Table 14. Alphabetic Pin Assignments. Pin s_ad<2> s_ad<3> s_ad<4> s_ad<5> s_ad<6> s_ad<7> s_ad<8> s_ad<9> s_ad<10> s_ad<11> s_ad<12> s_ad<13> s_ad<14> s_ad<15> s_ad<16> s_ad<17> s_ad<18> s_ad<19> s_ad<20> s_ad<21> s_ad<22> s_ad<23> s_ad<24> s_ad<25> s_ad<26> s_ad<27> s_ad<28> s_ad<29> s_ad<30> s_ad<31> s_cbe_l<0> s_cbe_l<1> s_cbe_l<2> s_cbe_l<3> ...
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Table 14. Alphabetic Pin Assignments. Pin s_vio tck tdi tdo tms trst_l vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd ...
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PCI Bus Operation This chapter presents detailed information about PCI transactions, transaction forwarding across the 21150, and transaction termination. 4.1 Types of Transactions This section provides a summary of PCI transactions performed by the 21150. Table 15 lists the ...
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PCI buses, either upstream or downstream, a Type 1 configuration command must be used. • The 21150 does not generate Type 0 configuration transactions on the primary interface, nor does it respond to Type ...
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The 21150 responds only to dual address transactions that use the following transaction command codes: • Memory write • Memory write and invalidate • Memory read • Memory read line • Memory read multiple Use of other transaction codes may ...
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Posted Write Transactions Posted write forwarding is used for memory write and for memory write and invalidate transactions. When the 21150 determines that a memory write transaction forwarded across the bridge, the 21150 asserts DEVSEL# ...
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Figure 6. Flow-Through Posted Memory Write Transaction CY0 Cycle CY1 < 15ns > p_clk p_ad Addr p_cbe_l 7 p_frame_l p_irdy_l p_devsel_l p_trdy_l p_stop_l s_clk s_ad s_cbe_l s_frame_l s_irdy_l s_devsel_l s_trdy_l s_stop_l The 21150 ends the transaction on the target bus ...
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Memory Write and Invalidate Transactions Posted write forwarding is used for memory write and invalidate transactions. Memory write and invalidate transactions guarantee transfer of entire cache lines. If the write buffer fills before an entire cache line is ...
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If the 21150 is unable to deliver write data after 2 attempts and returns a target abort to the initiator. The delayed transaction is removed from the delayed transaction queue. The 21150 also asserts p_serr_l if the primary SERR# enable ...
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Figure 7. Downstream Delayed Write Transaction CY0 Cycle < 15ns > p_clk p_ad p_cbe_l p_frame_l p_irdy_l p_devsel_l p_trdy_l p_stop_l s_clk s_ad s_cbe_l s_frame_l s_irdy_l s_devsel_l s_trdy_l s_stop_l The 21150 implements a discard timer that starts counting when the delayed ...
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Table 17. Write Transaction Disconnect Address Boundaries Type of Transaction Delayed write Posted memory write Posted memory write Posted memory write and invalidate Posted memory write and invalidate Posted memory write and invalidate 1. The memory write disconnect control bit ...
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Figure 8. Multiple Memory Write Transactions Posted and Initiated as Fast Back-to-Back Transactions on the Target Bus CY0 Cycle CY1 < 15ns > p_clk p_ad Addr1 p_cbe_l p_frame_l p_irdy_l p_devsel_l p_trdy_l p_stop_l s_clk s_ad s_cbe_l s_frame_l s_irdy_l s_devsel_l s_trdy_l ...
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Table 18. Read Transaction Prefetching (Sheet Memory read Memory read line Memory read multiple See Section 5.3 for detailed information about prefetchable and nonprefetchable address spaces. 4.6.1 Prefetchable Read Transactions A prefetchable read transaction is a read ...
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Read Prefetch Address Boundaries The 21150 imposes internal read address boundaries on read prefetching. When a read transaction reaches one of these aligned address boundaries, the 21150 stops prefetching data, unless the target signals a target disconnect before ...
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Delayed Read Completion with Target When the delayed read request reaches the head of the delayed transaction queue, and all previously queued posted write transactions have been delivered, the 21150 arbitrates for the target bus and initiates the read ...
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Figure 9. Nonprefetchable Delayed Read Transaction CY0 Cycle < 15ns > p_clk p_ad p_cbe_l p_frame_l p_irdy_l p_devsel_l p_trdy_l p_stop_l s_clk s_ad s_cbe_l s_frame_l s_irdy_l s_devsel_l s_trdy_l s_stop_l Figure 10 shows a prefetchable delayed read transaction. 40 CY2 CY4 CY6 ...
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Figure 10. Prefetchable Delayed Read Transaction CY0 Cycle CY1 < 15ns > p_clk p_ad Addr p_cbe_l 6 p_frame_l p_irdy_l p_devsel_l p_trdy_l p_stop_l s_clk s_ad s_cbe_l s_frame_l s_irdy_l s_devsel_l s_trdy_l s_stop_l When the master repeats the transaction and starts transferring prefetchable ...
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Figure 11. Flow-Through Prefetchable Read Transaction CY0 Cycle CY1 <15ns> p_clk p_ad Addr p_cbe_l 6 p_frame_l p_irdy_l p_devsel_l p_trdy_l p_stop_l s_clk s_ad s_cbe_l s_frame_l s_irdy_l s_devsel_l s_trdy_l s_stop_l The 21150 implements a discard timer that starts counting when the ...
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In addition to accepting configuration transactions for initialization of its own configuration space, the 21150 also forwards configuration transactions for device initialization in hierarchical PCI systems, as well as for special cycle generation. To support hierarchical PCI bus systems, two ...
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The 21150 limits all configuration accesses to a single Dword data transfer and returns a target disconnect with the first data transfer if additional data phases are requested. Because read transactions to 21150 configuration space do not have side ...
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Table 20. Device Number to IDSEL s_ad Pin Mapping Device p_ad<15:11> Number 0h 00000 1h 00001 2h 00010 3h 00011 4h 00100 5h 00101 6h 00110 7h 00111 8h 01000 9h 01001 Ah 01010 Bh 01011 Ch 01100 Dh 01101 ...
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The bus number falls in the range defined by the lower limit (exclusive) in the secondary bus number register and the upper limit (inclusive) in the subordinate bus number register. • The bus command is a configuration read ...
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Transaction Termination This section describes how the 21150 returns transaction termination conditions back to the initiator. The initiator can terminate transactions with one of the following types of termination: • Normal termination Normal termination occurs when the initiator deasserts ...
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If the 21150 is delivering posted write data when it terminates the transaction because the master latency timer expires, it initiates another transaction to deliver the remaining write data. The address of the transaction is updated to reflect the ...
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Figure 13. Delayed Write Transaction Terminated with Master Abort CY0 Cycle CY1 < 15ns > p_clk p_ad Addr p_cbe_l p_frame_l p_irdy_l p_devsel_l p_trdy_l p_stop_l s_clk s_ad s_cbe_l s_frame_l s_irdy_l s_devsel_l s_trdy_l s_stop_l When a master abort is received in response ...
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Target Termination Received by the 21150 When the 21150 initiates a transaction on the target bus and the target responds with DEVSEL#, the target can end the transaction with one of the following types of termination: • Normal ...
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Posted Write Target Termination Response When the 21150 initiates a posted write transaction, the target termination cannot be passed back to the initiator. Table 22 during a posted write transaction. Table 22. 21150 Response to Posted Write Target Termination ...
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Table 23. 21150 Response to Delayed Read Target Termination (Sheet Target abort Figure 14 shows a delayed read transaction that is terminated with a target abort. Figure 14. Delayed Read Transaction Terminated with Target Abort CY0 ...
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After the 21150 makes 2 21150 asserts p_serr_l if the primary SERR# enable bit is set in the command register and the implementation-specific p_serr_l disable bit for this condition is not set in the p_serr_l event disable register. The 21150 ...
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When a target retry is returned to the initiator of a delayed transaction, the initiator must repeat the transaction with the same address and bus command as well as the data if this is a write transaction, within the ...
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Address Decoding The 21150 uses three address ranges that control I/O and memory transaction forwarding. These address ranges are defined by base and limit address registers in the 21150 configuration space. This chapter describes these address ranges, as well ...
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Caution: If any 21150 configuration state affecting I/O transaction forwarding is changed by a configuration write operation on the primary bus at the same time that I/O transactions are ongoing on the secondary bus, the 21150 response to the ...
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The 16 bits contained in the I/O base upper 16 bits register at configuration offset 30h define AD<31:16> of the I/O base address. All 16 bits are read/write. After primary bus reset or chip reset, the value of the I/O ...
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Figure 16. I/O Transaction Forwarding in ISA Mode 5.3 Memory Address Decoding The 21150 has three mechanisms for defining memory address ranges for forwarding of memory transactions: • Memory-mapped I/O base and limit address registers • Prefetchable memory base ...
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PCI buses are idle. 5.3.1 Memory-Mapped I/O Base and Limit Address Registers Memory-mapped I/O is also referred to as nonprefetchable memory. Memory addresses that cannot automatically be ...
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Figure 17. Memory Transaction Forwarding Using Base and Limit Registers 5.3.2 Prefetchable Memory Base and Limit Address Registers Locations accessed in the prefetchable memory address range must have true memory-like behavior and must not exhibit side effects when read. ...
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The prefetchable memory address range has a granularity and alignment of 1MB. The maximum memory address range is 4GB when 32-bit addressing is used, and 2 addressing is used. The prefetchable memory address range is defined by a 16-bit prefetchable ...
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I/O or VGA memory range). A dual address memory transaction is forwarded downstream from the primary interface if it falls within the address range defined by the prefetchable memory base address, prefetchable memory base address upper ...
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The VGA I/O addresses consist of the following I/O addresses: • 3B0h–3BBh • 3C0h–3DFh These I/O addresses are aliased every 1KB throughout the first 64KB of I/O space. This means that address bits <15:10> are not decoded and can be ...
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Transaction Ordering To maintain data coherency and consistency, the 21150 complies with the ordering rules set forth in the PCI Local Bus Specification, Revision 2.1, for transactions crossing the bridge. This chapter describes the ordering rules that control transaction ...
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General Ordering Guidelines Independent transactions on the primary and secondary buses have a relationship only when those transactions cross the 21150. The following general ordering guidelines govern transactions crossing the 21150: • The ordering relationship of a transaction ...
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Table 24. Summary of Transaction Ordering (Sheet Pass Posted Write Delayed write No request Delayed read No completion Delayed write Yes completion The following ordering rules describe the transaction relationships. Each ordering rule is followed by an ...
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Data Synchronization Data synchronization refers to the relationship between interrupt signaling and data delivery. The PCI Local Bus Specification, Revision 2.1, provides the following alternative methods for synchronizing data and interrupts: • The device signaling the interrupt performs ...
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Error Handling The 21150 checks, forwards, and generates parity on both the primary and secondary interfaces. To maintain transparency, the 21150 always tries to forward the existing parity condition on one bus to the other bus, along with address ...
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The 21150 asserts p_serr_l and sets the signaled system error bit in the status register, if both of the following conditions are met: — The SERR# enable bit is set in the command register. — The parity error ...
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The 21150 asserts p_perr_l two cycles following the data transfer, if the primary interface parity error response bit is set in the command register • The 21150 sets the detected parity error bit in the primary status register. • ...
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The 21150 sets the secondary interface data parity detected bit in the secondary status register, if the secondary parity error response bit is set in the bridge control register. • The 21150 captures the parity error condition to ...
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For upstream transactions, in the case where the parity error is being passed back from the target bus and the initiator bus, the following events occur: • The 21150 asserts s_perr_l two cycles after the data transfer, if both of ...
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The 21150 asserts p_serr_l and sets the signaled system error bit in the status register, if all of the following conditions are met: — The SERR# enable bit is set in the command register. — The secondary interface ...
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Table 26. Setting the Secondary Interface Detected Parity Error Bit Secondary Detected Parity Error Bit 0 Read 1 Read 0 Read 0 Read 0 Posted write 0 Posted write 0 Posted write 1 Posted write 0 Delayed write 0 Delayed ...
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Table 28 shows setting the data parity detected bit in the secondary status register, corresponding to the secondary interface. This bit is set under the following conditions: • The 21150 must be a master on the secondary bus. • ...
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Table 29. Assertion of p_perr_l (Sheet p_perr_l 1 Posted write 1 Posted write 0 Delayed write 1 0 Delayed write 1 Delayed write 1 Delayed write don’t care Table 30 shows assertion of s_perr_l.. ...
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The parity error response bit on the command register and the parity error response bit on the bridge control register must both be set. • The SERR# enable bit must be set in the command register. Table 31. ...
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Parity error reported on target bus during posted write transaction (see previous section) • Delayed write data discarded after 2 • Delayed read data cannot be transferred from target after 2 received) • Master timeout on delayed transaction The ...
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Exclusive Access This chapter describes the use of the LOCK# signal to implement exclusive access to a target for transactions that cross the 21150. 8.1 Concurrent Locks The primary and secondary bus lock mechanisms operate concurrently except when a ...
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Note that the existing lock on the secondary bus could ...
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When the last locked transaction is a posted write transaction, the 21150 deasserts s_lock_l on the secondary bus at the end of the transaction because the lock was relinquished at the end of the write transaction on the primary bus. ...
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PCI Bus Arbitration The 21150 must arbitrate for use of the primary bus when forwarding upstream transactions, and for use of the secondary bus when forwarding downstream transactions. The arbiter for the primary bus resides external to the 21150, ...
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The secondary arbiter supports a programmable 2-level rotating algorithm. Two groups of masters are assigned, a high priority group and a low priority group. The low priority group as a whole represents one entry in the high priority group; ...
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To prevent bus contention, if the secondary PCI bus is idle, the arbiter never asserts one grant signal in the same PCI cycle in which it deasserts another. It deasserts one grant, and then asserts the next grant, no earlier ...
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General-Purpose I/O Interface The 21150 implements a 4-pin general-purpose I/O gpio interface. During normal operation, the gpio interface is controlled by device-specific configuration registers. In addition, the gpio interface can be used for the following functions: • During secondary ...
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Secondary Clock Control The 21150 uses the gpio pins and the msk_in signal to input a 16-bit serial data stream. This data stream is shifted into the secondary clock control register and is used for selectively disabling secondary ...
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The first 8 bits contain the PRSNT#<1:0> signal values for four slots, and these bits control the s_clk_o<3:0> outputs. If one or both of the PRSNT#<1:0> signals are 0, that indicates that a card is present in the slot and ...
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The 8 least significant bits are connected to the PRSNT# pins for the slots. The next 5 bits are tied high to disable their respective secondary clocks because those clocks are not connected to anything. The next bit is ...
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Once live insertion mode brings the 21150 to a halt and queued transactions are completed, the secondary reset bit in the bridge control register can be used to assert s_rst_l, if desired, to reset and tristate secondary bus devices, and ...
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Clocks This chapter provides information about the 21150 clocks. 11.1 Primary and Secondary Clock Inputs The 21150 implements a separate clock input for each PCI interface. The primary interface is synchronized to the primary clock input, p_clk, and the ...
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DIGITAL recommends using an equivalent amount of etch on the board for all secondary clocks, to minimize skew between them, and a maximum delay of the etch of 2 ns. • DIGITAL recommends terminating or disabling unused secondary ...
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Operation Some versions of the 21150 support 66 MHz operation. All 21150 versions marked 21150-Bx are 66MHz capable. Versions of the 21150 marked 21150-Ax are not capable of operation at 66 MHz. Signal config66 must be tied high ...
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PCI Power Management 1 The 21150 incorporates functionality that meets the requirements of the PCI Power Management Specification, Revision 1.0. These features include: • PCI Power Management registers using the Enhanced Capabilities Port (ECP) address mechanism • Support for ...
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Reset This chapter describes the primary interface, secondary interface, and chip reset mechanisms. 14.1 Primary Interface Reset The 21150 has one reset input, p_rst_l. When p_rst_l is asserted, the following events occur: • The 21150 immediately tristates all primary ...
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Chip Reset The chip reset bit in the diagnostic control register can be used to reset the 21150 and the secondary bus. When the chip reset bit is set, all registers and chip state are reset and all ...
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Configuration Space Registers This chapter provides a detailed description of the 21150 configuration space registers. The chapter is divided into three sections: configuration registers, and Section 15.3 describes the configuration register values after reset. The 21150 configuration space uses ...
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Figure 22. 21150 Configuration Space 31 Reserved Secondary Latency Timer Secondary Status Memory Limit Address Prefetchable Memory Limit Address I/O Limit Address Upper 16 Bits gpio Input Data Reserved Power Management Capabilities** Data * In the 21150-AA only, these ...
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PCI-to-PCI Bridge Standard Configuration Registers This section provides a detailed description of the PCI-to-PCI bridge standard configuration registers. Each field has a separate description. Fields that have the same configuration Dword address are selectable by turning on (driving low) ...
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Dword Bit 0 I/O space enable 1 Memory space enable 2 Master enable 3 Special cycle enable Memory write and 4 invalidate enable 5 VGA snoop enable 106 Name R/W Controls the 21150’s response to I/O transactions on the ...
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Dword Bit 6 Parity error response 7 Wait cycle control 8 SERR# enable 9 Fast back-to-back enable 15;10 Reserved 15.1.4 Primary Status Register—Offset 06h This section describes the primary status register. These bits affect the status of the 21150 primary ...
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Dword Bit 19:16 Reserved 20 ECP 21 66-MHz capable 22 Reserved Fast back-to-back 23 capable 24 Data parity detected 26:25 DEVSEL# timing 27 Signaled target abort 28 Received target abort 29 Received master abort 30 Signaled system error 31 ...
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Revision ID Register—Offset 08h This section describes the revision ID register. Dword address = 08h Byte enable p_cbe_l<3:0> = xxx0b Dword Bit 7:0 Revision ID 15.1.6 Programming Interface Register—Offset 09h This section describes the programming interface register. Dword address ...
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Cache Line Size Register—Offset 0Ch This section describes the cache line size register. Dword address = 0Ch Byte enable p_cbe_l<3:0> = xxx0b Dword Bit 7:0 Cache line size 15.1.10 Primary Latency Timer Register—Offset 0Dh This section describes the ...
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Primary Bus Number Register—Offset 18h This section describes the primary bus number register. This register must be initialized by configuration software. Dword address = 18h Byte enable p_cbe_l<3:0> = xxx0b Dword Bit 7:0 Primary bus number 15.1.13 Secondary Bus ...
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Dword Bit 23:16 Subordinate bus number 15.1.15 Secondary Latency Timer Register—Offset 1Bh This section describes the secondary latency timer register. Dword address = 18h Byte enable p_cbe_l<3:0> = 0xxxb Dword Bit 31:24 Secondary latency timer 15.1.16 I/O Base Address ...
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Dword Bit 3:0 32-bit indicator 7:4 I/O base address <15:12> R/W 15.1.17 I/O Limit Address Register—Offset 1Dh This section describes the I/O limit address register. This register must be initialized by configuration software. Dword address = 1Ch Byte enable p_cbe_l<3:0> ...
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Dword Bit 20:16 Reserved 21 66-MHz capable 22 Reserved Fast back-to-back 23 capable 24 Data parity detected 26:25 DEVSEL# timing 27 Signaled target abort 28 Received target abort 29 Received master abort 30 Received system error 31 Detected parity ...
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Memory Base Address Register—Offset 20h This section describes the memory base address register. This register must be initialized by configuration software. Dword address = 20h Byte enable p_cbe_l<3:0> = xx00b Dword Bit 3:0 Reserved Memory base address 15:4 <31:20> ...
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Dword Bit 3:0 64-bit indicator Prefetchable memory 15:4 base address <31:20> 15.1.22 Prefetchable Memory Limit Address Register—Offset 26h This section describes the prefetchable memory limit address register. This register must be initialized by configuration software. Dword address = 24h ...
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Dword Bit Upper 32 prefetchable 31:0 memory base address <63:32> 15.1.24 Prefetchable Memory Limit Address Upper 32 Bits Register—Offset 2Ch This section describes the prefetchable memory limit address upper 32 bits register. This register must be initialized by configuration software. ...
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I/O Limit Address Upper 16 Bits Register—Offset 32h This section describes the I/O limit address upper 16 bits register. This register must be initialized by configuration software. Dword address = 30h Byte enable p_cbe_l<3:0> = 00xxb Dword Bit ...
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Subsystem ID Register—Offset 36h This section describes the subsystem ID register. Dword address = 34h Byte enable p_cbe_l<3:0> = 00xxb Dword Bit 31:16 Subsystem ID 15.1.30 Interrupt Pin Register—Offset 3Dh This section describes the interrupt pin register. Dword address ...
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Dword Bit 17 SERR# forward enable 18 ISA enable 19 VGA enable 20 Reserved 120 Name R/W Controls whether the 21150 asserts p_serr_l when it detects s_serr_l asserted. When 0—The 21150 does not drive p_serr_l in response to s_serr_l ...
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Dword Bit 21 Master abort mode 22 Secondary bus reset 23 Fast back-to-back enable 24 Primary master timeout Preliminary Datasheet Name R/W Controls the 21150’s behavior when a master abort termination occurs in response to a transaction initiated by the ...
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Dword Bit Secondary master 25 timeout 26 Master timeout status Master timeout SERR# 27 enable 31:28 Reserved 15.1.32 Capability ID Register—Offset DCh This section describes the capability ID register. (Implemented in the 21150-AB and later revisions only. In the ...
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Next Item Ptr Register—Offset DDh This section describes the next item ptr register. (Implemented in the 21150-AB and later revisions only. In the 21150-AA, these registers are reserved.) Dword address = DCh Byte enable p_cbe_l<3:0> = xx0xb Dword Bit ...
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Power Management Control and Status Register—Offset E0h This section describes the power management control and status register. (Implemented in the 21150-AB and later revisions only. In the 21150-AA, these registers are reserved.) Dword address = E0h Byte enable ...
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Dword Bit 23 BPCC_EN 15.1.37 Data Register—Offset E3h This section describes the data register. Dword address = E0h Byte enable p_cbe_l<3:0> = 0xxxb Dword Bit 31:24 Data 15.2 Device-Specific Configuration Registers This section provides a detailed description of the 21150 ...
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Dword Bit 0 Reserved Memory write disconnect 1 control 3:2 Reserved Secondary bus prefetch 4 disable 5 Live insertion mode 7:6 Reserved 15.2.2 Diagnostic Control Register—Offset 41h This section describes the diagnostic control register. W1TR indicates that writing 1 ...
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Dword Bit 8 Chip reset 10:9 Test mode 15:11 Reserved 15.2.3 Arbiter Control Register—Offset 42h This section describes the arbiter control register. Dword address = 40h Byte enablep_cbe_l<3:0> = 00xxb Dword Bit 25:16 Arbiter control 31:26 Reserved Preliminary Datasheet Name ...
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Event Disable Register—Offset 64h This section describes the p_serr_l event disable register. Dword address = 64h Byte enable p_cbe_l<3:0> = xxx0b Dword Bit 0 Reserved 1 Posted write parity error 2 Posted write nondelivery Target abort during ...
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Dword Bit 5 Delayed write nondelivery Delayed read—no data 6 from target 7 Reserved 15.2.5 gpio Output Data Register—Offset 65h This section describes the gpio output data register. Dword address = 64h Byte enable p_cbe_l<3:0> = xx0xb Dword Bit GPIO ...
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Output Enable Control Register—Offset 66h This section describes the gpio output enable control register. Dword address = 64h Byte enable p_cbe_l<3:0> = x0xxb Dword Bit GPIO output enable write- 19:16 1-to-clear GPIO output enable write- 23:20 1-to-set ...
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Dword Bit 1:0 Slot 0 clock disable 3:2 Slot 1 clock disable 5:4 Slot 2 clock disable 7:6 Slot 3 clock disable 8 Device 1 clock disable 9 Device 2 clock disable 10 Device 3 clock disable 11 Device 4 ...
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Dword Bit 13 The 21150 clock disable 15:14 Reserved 15.2.9 p_serr_l Status Register—Offset 6Ah This section describes the p_serr_l status register. This status register indicates the reason for the 21150’s assertion of p_serr_l. Dword address = 68h Byte enable ...
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Dword Bit 21 Delayed write nondelivery Delayed read—no data 22 from target Delayed transaction 23 master timeout 15.3 Configuration Register Values After Reset Table 35 lists the value of the 21150 configuration registers after reset. Reserved registers are not listed ...
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Table 35. Configuration Register Values After Reset (Sheet Byte Address 26–27h 28–2Bh 2C–2Fh 30–31h 32–33h 34–35h 36–37h 3Dh 3E–3Fh 40h 41h 42–43h 64h 65h 66h 67h 68–69h 6Ah DCh DDh DE–DFh E0–E1h E2h E3h 1. Dependent ...
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JTAG Test Port This chapter describes the 21150’s implementation of a joint test action group (JTAG) test port according to IEEE Standard 1149.1, IEEE Standard Test Access Port and Boundary-Scan Architecture. 16.1 Overview The 21150 contains a serial-scan test ...
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Instruction Register The 5-bit instruction register selects the test modes and features.The instruction register bits are interpreted as instructions, as shown in of the boundary-scan and bypass registers. Table 37 describes the 21150’s instructions. Table 37. JTAG Instruction ...
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Boundary-Scan Register Cells Each boundary-scan cell operates in conjunction with the current instruction and the current state in the test access port controller state machine. The function of the BSR cells is determined by the associated pins, as follows: ...
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Table 38. Boundary-Scan Order (Sheet Pin Signal Name Number 15 s_gnt_l<4> 16 s_gnt_l<5> 17 s_gnt_l<6> 18 s_gnt_l<7> 19 s_gnt_l<8> 21 s_clk 22 s_rst_l 23 s_cfn_l 24 gpio<3> 25 gpio<2> 27 gpio<1> 28 gpio<0> 29 s_clk_o<0> 30 ...
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Table 38. Boundary-Scan Order (Sheet Pin Signal Name Number 65 p_isdel 67 p_ad<23> 68 p_ad<22> 70 p_ad<21> 71 p_ad<20> 73 p_ad<19> 74 p_ad<18> 76 p_ad<17> 77 p_ad<16> 79 p_cbe_l<2> 80 p_frame_l 82 p_irdy_l 83 p_trdy_l 84 p_devsel_l ...
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Table 38. Boundary-Scan Order (Sheet Pin Signal Name Number 119 p_ad<2> 121 p_ad<1> 122 p_ad<0> 125 config66 126 msk_in tdi tdo 137 s_ad<0> 138 s_ad<1> 140 s_ad<2> 141 s_ad<3> 143 s_ad<4> 144 s_ad<5> 146 s_ad<6> 147 ...
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Table 38. Boundary-Scan Order (Sheet Pin Signal Name Number 179 s_frame_l 180 s_cbe_l<2> 182 s_ad<16> 183 s_ad<17> 185 s_ad<18> 186 s_ad<19> 188 s_ad<20> 189 s_ad<21> 191 s_ad<22> 192 s_ad<23> 194 s_cbe_l<3> 195 s_ad<24> 197 s_ad<25> 198 s_ad<26> ...
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Electrical Specifications This chapter specifies the following electrical behavior of the 21150: • PCI electrical conformance • Absolute maximum ratings • dc specifications • ac timing specifications 17.1 PCI Electrical Specification Conformance The 21150 PCI pins conform to the ...
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DC Specifications Table 41 defines the dc parameters met by all 21150 signals under the conditions of the functional operating range. Table 41. DC Parameters Symbol V Supply voltage cc Low-level input V il voltage High-level input V ...
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Clock Timing Specifications The ac specifications consist of input requirements and output responses. The input requirements consist of setup and hold times, pulse widths, and high and low times. Output responses are delays from clock to signal. The ac ...
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Table 42. 33 MHz PCI Clock Signal AC Parameters (Sheet Symbol p_clk falling to T sclkf s_clk_o falling s_clk_0 duty cycle skew T dskew from p_clk duty cycle s_clk_0<x> skew s_clk_0<y> 1. 0.2 V ...
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Figure 24. PCI Signal Timing Measurement Conditions Table 44. 33 MHz PCI Signal Timing Symbol CLK to signal valid delay— T val bused signals CLK to signal valid delay— T val(ptp) point-to- point Float to active T on delay Active ...
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Table 45. 66 MHz PCI Signal Timing Symbol CLK to signal valid delay— T val bused signals CLK to signal valid delay— T val(ptp) point-to- point Float to active T on delay Active to float T off delay Input ...
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Table 46. Reset Timing Specifications (Sheet Symbol s_rst_l active T time after s_clk srst-on stable s_rst_l deassertion T dsrst after p_rst_l deassertion p_rst_l slew rate 1. Applies to rising (deasserting) edge only. 17.4.4 gpio Timing Specifications Table ...
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Table 48. 66 MHz gpio Timing Specifications Symbol s_clk-to-gpio T vgpio output valid gpio float-to- T gon active delay gpio active-to- T goff float delay gpio-to-s_clk T gsu setup time gpio hold time T gh after s_clk s_clk-to- gpio<0> ...
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Table 49. JTAG Timing Specifications (Sheet Symbol tdi, tms hold T time from tck jh rising edge tdo valid delay T from tck falling jd edge tdo float delay T from tck falling jfd edge 1. Measured ...
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Mechanical Specifications The 21150 is contained in an industry-standard 208-pin plastic quad flat pack (PQFP) package, shown in Figure 25. Figure 25. 208-Pin PQFP Package (A) A2 Detail "A" Preliminary Datasheet - Pin 1 208-Pin ...
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Table 50 lists the 208-pin package dimensions in millimeters. Table 50. 208-Pin PQFP Package Dimensions Symbol LL Lead Length e Lead pitch L Foot length A Package overall height 1 A1 Package standoff height 2 A2 Package thickness b ...
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