AT32UC3A0512 Atmel Corporation, AT32UC3A0512 Datasheet - Page 278
AT32UC3A0512
Manufacturer Part Number
AT32UC3A0512
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(98 pages)
2.AT32UC3A0128.pdf
(826 pages)
3.AT32UC3A0128.pdf
(377 pages)
4.AT32UC3A0128.pdf
(33 pages)
5.AT32UC3A0128.pdf
(159 pages)
Specifications of AT32UC3A0512
Flash (kbytes)
512 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
109
Ext Interrupts
109
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
1
Uart
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
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32058K AVR32-01/12
25.9.3
Name:
Access Type:
Offset:
Reset value:
• PERIOD: Receive Period Divider Selection
This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync Signal. If 0, no
PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD+1) Receive Clock.
• STTDLY: Receive Start Delay
If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception.
When the Receiver is programmed to start synchronously with the Transmitter, the delay is also applied.
Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG
(Receive Sync Data) reception.
• STOP: Receive Stop Selection
0: After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a
new compare 0.
1: After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected.
• START: Receive Start Selection
0x9-0xF
START
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
31
23
15
–
7
Receive Clock Mode Register
CKG
Continuous, as soon as the receiver is enabled, and immediately after the end of
transfer of the previous data.
Transmit start
Detection of a low level on RX_FRAME_SYNC signal
Detection of a high level on RX_FRAME_SYNC signal
Detection of a falling edge on RX_FRAME_SYNC signal
Detection of a rising edge on RX_FRAME_SYNC signal
Detection of any level change on RX_FRAME_SYNC signal
Detection of any edge on RX_FRAME_SYNC signal
Compare 0
Reserved
Receive Start
30
22
14
RCMR
Read/Write
0x10
0x00000000
–
6
CKI
29
21
13
–
5
STOP
28
20
12
4
PERIOD
STTDLY
CKO
27
19
11
3
26
18
10
2
START
25
17
9
1
AT32UC3A
CKS
24
16
8
0
278
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