AT32UC3A0512 Atmel Corporation, AT32UC3A0512 Datasheet - Page 385
AT32UC3A0512
Manufacturer Part Number
AT32UC3A0512
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(98 pages)
2.AT32UC3A0128.pdf
(826 pages)
3.AT32UC3A0128.pdf
(377 pages)
4.AT32UC3A0128.pdf
(33 pages)
5.AT32UC3A0128.pdf
(159 pages)
Specifications of AT32UC3A0512
Flash (kbytes)
512 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
109
Ext Interrupts
109
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
1
Uart
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
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32058K AVR32-01/12
27.6.5.2
Early Read Wait State
In some cases, the SMC inserts a wait state cycle between a write access and a read access to
allow time for the write cycle to end before the subsequent read cycle begins. This wait state is
not generated in addition to a chip select wait state. The early read cycle thus only occurs
between a write and read access to the same memory device (same chip select).
• An early read wait state is automatically inserted if at least one of the following conditions is
• if the write controlling signal has no hold time and the read controlling signal has no setup time
• in NCS write controlled mode (WRITE_MODE = 0), if there is no hold timing on the NCS signal
• in NWE controlled mode (WRITE_MODE = 1) and if there is no hold timing (NWE_HOLD = 0),
Figure 27-18. Early Read Wait State: Write with No Hold Followed by Read with No Setup.
valid:
(Figure
and the NCS_RD_SETUP parameter is set to 0, regardless of the read mode
The write operation must end with a NCS rising edge. Without an Early Read Wait State, the
write operation could not complete properly.
the feedback of the write control signal is used to control address, data, chip select and byte
select lines. If the external write control signal is not inactivated as expected due to load
capacitances, an Early Read Wait State is inserted and address, data and control signals are
maintained one more cycle. See
NBS0, NBS1,
A0, A1
27-18).
CLK_SMC
A[25:2]
D[15:0]
NWE
NRD
Write cycle
Figure
No hold
27-20.
Early Read
Wait state
No setup
Read cycle
AT32UC3A
(Figure
27-19).
385
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