AT32UC3A1256 Atmel Corporation, AT32UC3A1256 Datasheet - Page 756
AT32UC3A1256
Manufacturer Part Number
AT32UC3A1256
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(98 pages)
2.AT32UC3A0128.pdf
(826 pages)
3.AT32UC3A0128.pdf
(377 pages)
4.AT32UC3A0128.pdf
(33 pages)
5.AT32UC3A0128.pdf
(159 pages)
Specifications of AT32UC3A1256
Flash (kbytes)
256 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
69
Ext Interrupts
69
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
1
Uart
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A1256-U
Manufacturer:
ATMEL
Quantity:
496
- AT32UC3A0128 PDF datasheet
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32058K AVR32-01/12
36.9.7
CANCEL_ACCESS
For write operations, 32 data bits must be provided, or the result will be undefined. For read
operations, shifting may be terminated once the required number of bits have been acquired.
Table 36-10. MEMORY_BLOCK_ACCESS details
The overhead using block word access is 4 cycles per 32 bits of data, resulting in an 88% trans-
fer efficiency, or 2.1 MBytes per second with a 20 MHz TCK frequency.
If a very slow memory location is accessed during a SAB memory access, it could take a very
long time until the busy bit is cleared, and the SAB becomes ready for the next operation. The
CANCEL_ACCESS instruction provides a possibility to abort an ongoing transfer and report a
timeout to the user.
When the CANCEL_ACCESS instruction is selected, the current access will be terminated as
soon as possible. There are no guarantees about how long this will take, as the hardware may
not always be able to cancel the access immediately. The SAB is ready to respond to a new
command when the busy bit clears.
Table 36-11. CANCEL_ACCESS details
Instructions
IR input value
IR output value
DR Size
DR input value (Data read phase)
DR input value (Data write phase)
DR output value (Data read phase)
DR output value (Data write phase)
Instructions
IR input value
IR output value
DR Size
DR input value
DR output value
1. Use the MEMORY_SIZE_ACCESS or MEMORY_WORD_ACCESS to read or write the
2. Apply MEMORY_BLOCK_ACCESS in the IR Scan path.
3. Select the DR Scan path. The address will now have incremented by 1, 2, or 4 (corre-
4. For a read operation, scan out the contents of the next addressed location. For a write
5. Go to Update-DR.
6. If the block access is not complete, return to Select-DR Scan and repeat the access.
7. If the block access is complete, return to Run-Test/Idle.
first location.
sponding to the next byte, halfword, or word location).
operation, scan in the new contents of the next addressed location.
Details
10010 (0x12)
peb01
34 bits
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xx
dddddddd dddddddd dddddddd dddddddd xx
eb dddddddd dddddddd dddddddd dddddddd
xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
Details
10011 (0x13)
peb01
1
x
0
AT32UC3A
756
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