AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 110

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AT32UC3A3128

Manufacturer Part Number
AT32UC3A3128
Description
Manufacturer
Atmel Corporation

Specifications of AT32UC3A3128

Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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11
9.3.5
Table 9-5.
110
Mnemonics
and
and{cond4}
andn
andh
andl
com
eor
eor{cond4}
eorh
eorl
or
or{cond4}
orh
orl
tst
AVR32
Logic Operations
Logic Operations
C
E
E
E
C
E
E
E
E
C
C
E
E
E
E
E
C
E
E
E
E
E
C
Operands / Syntax
Rd, Rs
Rd, Rx, Ry << sa
Rd, Rx, Ry >> sa
Rd, Rx, Ry
Rd, Rs
Rd, imm
Rd, imm, COH
Rd, imm
Rd, imm, COH
Rd
Rd, Rs
Rd, Rx, Ry << sa
Rd, Rx, Ry >> sa
Rd, Rx, Ry
Rd, imm
Rd, imm
Rd, Rs
Rd, Rx, Ry << sa
Rd, Rx, Ry >> sa
Rd, Rx, Ry
Rd, imm
Rd, imm
Rd, Rs
Description
Logical AND.
Logical AND if condition satisfied.
Logical AND NOT.
Logical AND High Halfword, low halfword is
unchanged.
Logical AND High Halfword, clear other
halfword.
Logical AND Low Halfword, high halfword
is unchanged.
Logical AND Low Halfword, clear other
halfword.
One’s Complement (NOT).
Logical Exclusive OR.
Logical EOR if condition satisfied.
Logical Exclusive OR
(High Halfword).
Logical Exclusive OR
(Low Halfword).
Logical (Inclusive) OR.
Logical OR if condition satisfied.
Logical OR (High Halfword).
Logical OR (Low Halfword).
Test register for zero.
Operation
Rd ← Rd ∧ Rs
Rd ← Rx ∧ (Ry << sa5)
Rd ← Rx ∧ (Ry >> sa5)
if (cond4) Rd ← Rx ∧ Ry
Rd ← Rd ∧ ¬Rs
Rd[31:16] ← Rd[31:16] ∧ imm16
Rd[31:16] ← Rd[31:16] ∧ imm16
Rd[15:0] ← 0
Rd[15:0] ← Rd[15:0] ∧ imm16
Rd[15:0] ← Rd[15:0] ∧ imm16
Rd[31:16] ← 0
Rd ← ¬Rd
Rd ← Rd ⊕ Rs
Rd ← Rd ⊕ (Rs << sa5)
Rd ← Rd ⊕ (Rs >> sa5)
if (cond4) Rd ← Rx ⊕ Ry
Rd[31:16] ← Rd[31:16] ⊕ imm16
Rd[15:0] ← Rd[15:0] ⊕ imm16
Rd ← Rd ∨ Rs
Rd ← Rd ∨ (Rs << sa5)
Rd ← Rd ∨ (Rs >> sa5)
if (cond4) Rd ← Rx ∨ Ry
Rd[31:16] ← Rd[31:16] ∨ imm16
Rd[15:0] ← Rd[15:0] ∨ imm16
Rd ∧ Rs
32000D–04/2011
Rev
1
1
1
2
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1

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