AT32UC3A4128S Atmel Corporation, AT32UC3A4128S Datasheet - Page 825
AT32UC3A4128S
Manufacturer Part Number
AT32UC3A4128S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A4128S
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 825 of 1012
- Download datasheet (16Mb)
AT32UC3A3/A4
In write operation, the Padding Value bit in the MR register (MR.PADV) is used to define the
padding value when writing non-multiple block size. When the MR.PADV is zero, then 0x00
value is used when padding data, otherwise 0xFF is used.
Write a one in the DMA Hardware Handshaking Enable bit in the DMA Configuration Register
(DMA.DMAEN) enables DMA transfer.
The following flowchart shows how to write a single block with or without use of DMA facilities
(see
Figure 30-11 on page
826). Polling or interrupt method can be used to wait for the end of
write according to the contents of the Interrupt Mask Register (IMR).
825
32072G–11/2011
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