AT32UC3B0512AU Atmel Corporation, AT32UC3B0512AU Datasheet - Page 228

• Manufacturer Part Number: AT32UC3B0512AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B0512AU

• Flash (kbytes): 512 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 44
• Ext Interrupts: 44
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 4
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.11.3
32059L–AVR32–01/2012
Read-write Flowcharts
The following flowcharts shown in
read and write operations. A polling or interrupt method can be used to check the status bits.
The interrupt method requires that the interrupt enable register (IER) be configured first.
Figure 19-14. TWI Write Operation with Single Data Byte without Internal Address.
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
- Device slave address (DADR)
Set the Master Mode register:
TWI_CR = MSEN + SVDIS
Write ==> bit MREAD = 0
TWI_THR = Data to send
Figure 19-14
Set the Control register:
Load Transmit register
- Transfer direction bit
Read Status register
Read Status register
(Needed only once)
Transfer finished
- Master enable
TXCOMP = 1?
Set TWI clock
TXRDY = 1?
Yes
Yes
BEGIN
to
Figure 19-19 on page 233
No
No
give examples for
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