AT90CAN64 Automotive Atmel Corporation, AT90CAN64 Automotive Datasheet - Page 198
AT90CAN64 Automotive
Manufacturer Part Number
AT90CAN64 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(431 pages)
2.AT90CAN128_AUTOMOTIVE.pdf
(16 pages)
3.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
Specifications of AT90CAN64 Automotive
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
8
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
2
Can
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
8
Input Capture Channels
2
Pwm Channels
7
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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17.11.9
17.11.10 USART1 Baud Rate Registers – UBRR1L and UBRR1H
198
AT90CAN32/64/128
USART0 Baud Rate Registers – UBRR0L and UBRR0H
• Bit 2:1 – UCSZn1:0: Character Size
The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits
(Character SiZe) in a frame the Receiver and Transmitter use.
Table 17-7.
• Bit 0 – UCPOLn: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is
used. The UCPOLn bit sets the relationship between data output change and data input sample,
and the synchronous clock (XCKn).
Table 17-8.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
UCPOLn
UCSZn2
0
1
0
0
0
0
1
1
1
1
UCSZn Bits Settings
UCPOLn Bit Settings
Transmitted Data Changed
(Output of TxDn Pin)
Rising XCK Edge
Falling XCK Edge
R/W
R/W
15
15
R
R
–
7
0
0
–
7
0
0
R/W
R/W
14
14
R
R
–
6
0
0
–
6
0
0
UCSZn1
0
0
1
1
0
0
1
1
R/W
R/W
13
13
R
R
–
5
0
0
–
5
0
0
R/W
R/W
12
12
R
R
–
4
0
0
–
4
0
0
UBRR0[7:0]
UBRR1[7:0]
UCSZn0
R/W
R/W
R/W
R/W
11
11
3
0
0
3
0
0
0
1
0
1
0
1
0
1
R/W
R/W
R/W
R/W
10
10
UBRR0[11:8]
UBRR1[11:8]
2
0
0
2
0
0
Received Data Sampled
(Input on RxDn Pin)
Falling XCK Edge
Rising XCK Edge
Character Size
5-bit
6-bit
7-bit
8-bit
Reserved
Reserved
Reserved
9-bit
R/W
R/W
R/W
R/W
9
1
0
0
9
1
0
0
R/W
R/W
R/W
R/W
8
0
0
0
8
0
0
0
UBRR0H
UBRR1H
UBRR0L
UBRR1L
7682C–AUTO–04/08
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