ATmega128A Atmel Corporation, ATmega128A Datasheet - Page 20

• Manufacturer Part Number: ATmega128A
• Manufacturer: Atmel Corporation

Specifications of ATmega128A

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7.2.1
8151H–AVR–02/11
Data Memory Access Times
The five different addressing modes for the data memory cover: Direct, Indirect with Displace-
ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register file,
registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base address given
by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O registers, and the 4096bytes of internal data
SRAM in the Atmel
The Register file is described in
Figure 7-2.
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
Data Memory Map
Memory Configuration A
64 I/O Registers
160 Ext I/O Reg.
®
External SRAM
Internal SRAM
Data Memory
AVR
32 Registers
(0 - 64K x 8)
(4096 x 8)
®
ATmega128A are all accessible through all these addressing modes.
“General Purpose Register File” on page
$10FF
$1100
$FFFF
$0000 - $001F
$0020 - $005F
$0060 - $00FF
$0100
CPU
Memory Configuration B
cycles as described in
64 I/O Registers
External SRAM
Internal SRAM
Data Memory
32 Registers
(0 - 64K x 8)
(4000 x 8)
ATmega128A
$0FFF
$1000
$0000 - $001F
$0020 - $005F
$0060
$FFFF
11.
Figure
7-3.
20