ATmega168A Atmel Corporation, ATmega168A Datasheet - Page 20

no-image

ATmega168A

Manufacturer Part Number
ATmega168A
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega168A

Flash (kbytes)
16 Kbytes
Pin Count
32
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
23
Ext Interrupts
24
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATmega168A-AU
Manufacturer:
ATMEL
Quantity:
464
Part Number:
ATmega168A-AU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATmega168A-AUR
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATmega168A-CCU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATmega168A-CCUR
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATmega168A-PU
Manufacturer:
ATMEL
Quantity:
1 000
8.3.1
8.4
8.4.1
8271D–AVR–05/11
EEPROM Data Memory
Data Memory Access Times
EEPROM Read/Write Access
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
Figure 8-4.
The ATmega48A/PA/88A/PA/168A/PA/328/P contains 256/512/512/1Kbytes of data EEPROM
memory. It is organized as a separate data space, in which single bytes can be read and written.
The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between
the EEPROM and the CPU is described in the following, specifying the EEPROM Address Reg-
isters, the EEPROM Data Register, and the EEPROM Control Register.
”Memory Programming” on page 297
in SPI or Parallel Programming mode.
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in
lets the user software detect when the next byte can be written. If the user code contains instruc-
tions that write the EEPROM, some precautions must be taken. In heavily filtered power
supplies, V
period of time to run at a voltage lower than specified as minimum for the clock frequency used.
See
situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
”Preventing EEPROM Corruption” on page 21
CC
Address
clk
is likely to rise or fall slowly on power-up/down. This causes the device for some
On-chip Data SRAM Access Cycles
Data
Data
WR
CPU
RD
ATmega48A/PA/88A/PA/168A/PA/328/P
Compute Address
T1
Memory Access Instruction
contains a detailed description on EEPROM Programming
Address valid
CPU
for details on how to avoid problems in these
T2
Table
cycles as described in
8-2. A self-timing function, however,
Next Instruction
T3
Figure
8-4.
20