ATtiny4 Atmel Corporation, ATtiny4 Datasheet - Page 64
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ATtiny4
Manufacturer Part Number
ATtiny4
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny4
Flash (kbytes)
0.5 Kbytes
Pin Count
6
Max. Operating Frequency
12 MHz
Cpu
8-bit AVR
# Of Touch Channels
1
Hardware Qtouch Acquisition
No
Max I/o Pins
4
Ext Interrupts
4
Usb Speed
No
Usb Interface
No
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.03
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
1
Output Compare Channels
2
Input Capture Channels
1
Pwm Channels
2
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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11.8.3
64
ATtiny4/5/9/10
Fast PWM Mode
The timing diagram for the CTC mode is shown in
(TCNT0) increases until a compare match occurs with either OCR0A or ICR0, and then counter
(TCNT0) is cleared.
Figure 11-8. CTC Mode, Timing Diagram
An interrupt can be generated at each time the counter value reaches the TOP value by either
using the OCF0A or ICF0 flag according to the register used to define the TOP value. If the inter-
rupt is enabled, the interrupt handler routine can be used for updating the TOP value. However,
changing the TOP to a value close to BOTTOM when the counter is running with none or a low
prescaler value must be done with care since the CTC mode does not have the double buffering
feature. If the new value written to OCR0A or ICR0 is lower than the current value of TCNT0, the
counter will miss the compare match. The counter will then have to count to its maximum value
(0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. In many
cases this feature is not desirable. An alternative will then be to use the fast PWM mode using
OCR0A for defining TOP (WGM03:0 = 15) since the OCR0A then will be double buffered.
For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical
level on each compare match by setting the Compare Output mode bits to toggle mode
(COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for
the pin is set to output (DDR_OC0A = 1). The waveform generated will have a maximum fre-
quency of
by the following equation:
The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOV0 flag is set in the same timer clock cycle that the
counter counts from MAX to 0x0000.
The fast Pulse Width Modulation or fast PWM mode (WGM03:0 = 5, 6, 7, 14, or 15) provides a
high frequency PWM waveform generation option. The fast PWM differs from the other PWM
options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts
from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC0x) is cleared
on the compare match between TCNT0 and OCR0x, and set at BOTTOM. In inverting Compare
Output mode output is set on compare match and cleared at BOTTOM. Due to the single-slope
TCNTn
OCnA
(Toggle)
Period
0
A
= f
clk_I/O
1
/2 when OCR0A is set to zero (0x0000). The waveform frequency is defined
f
OCnA
2
=
---------------------------------------------------
2 N
3
⋅
⋅
(
f
1
clk_I/O
+
Figure 11-8 on page
4
OCRnA
)
64. The counter value
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
(COMnA1:0 = 1)
8127E–AVR–11/11