ATtiny85 Atmel Corporation, ATtiny85 Datasheet
ATtiny85
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... ATtiny25/45/85: 0 – 10 MHz @ 2.7 - 5.5V MHz @ 4.5 - 5.5V • Industrial Temperature Range • Low Power Consumption – Active Mode: • 1 MHz, 1.8V: 300 µA – Power-down Mode: • 0.1 µA at 1.8V ® 8-Bit Microcontroller 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash ATtiny25/V ATtiny45/V ATtiny85/V Summary Rev. 2586NS–AVR–04/11 ...
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Pin Configurations Figure 1-1. Pinout ATtiny25/45/85 (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3 (PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4 (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3 (PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4 NOTE: Bottom pad should be soldered to ground. DNC: Do Not Connect 1.1 Pin Descriptions 1.1.1 VCC Supply voltage. 1.1.2 GND ...
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The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny25/45/85 as listed in “Alternate Functions ...
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Overview The ATtiny25/45/ low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny25/45/85 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to ...
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The resulting architecture is more code efficient while achieving throughputs up to ten times faster than con- ventional CISC microcontrollers. The ATtiny25/45/85 provides the following features: 2/4/8K ...
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About 3.1 Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. ...
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Register Summary Address Name Bit 7 0x3F SREG I 0x3E SPH – 0x3D SPL SP7 0x3C Reserved 0x3B GIMSK – 0x3A GIFR – 0x39 TIMSK – 0x38 TIFR – 0x37 SPMCSR – 0x36 Reserved 0x35 MCUCR BODS 0x34 MCUSR ...
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Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI ...
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Instruction Set Summary Mnemonics Operands ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract ...
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Mnemonics Operands ASR Rd Arithmetic Shift Right SWAP Rd Swap Nibbles BSET s Flag Set BCLR s Flag Clear BST Rr, b Bit Store from Register to T BLD Rd, b Bit load from T to Register SEC Set Carry ...
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Ordering Information 6.1 ATtiny25 (1) Speed (MHz) Supply Voltage (V) 10 1.8 – 5.5 20 2.7 – 5.5 Notes: 1. For speed vs. supply voltage, see section 2. All packages are Pb-free, halide-free and fully green, and they comply ...
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ATtiny45 (1) Speed (MHz) Supply Voltage (V) 10 1.8 – 5.5 20 2.7 – 5.5 Notes: 1. For speed vs. supply voltage, see section 2. All packages are Pb-free, halide-free and fully green and they comply with the European ...
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... Temperature Range Package 8P3 Industrial 8S2 (4) (-40°C to +85°C) 20M1 8P3 Industrial 8S2 (4) (-40°C to +85°C) 20M1 21.3 “Speed” on page 168. Package Types ATtiny25/45/85 (2) (3) Ordering Code ATtiny85V-10PU ATtiny85V-10SU ATtiny85V-10SUR ATtiny85V-10SH ATtiny85V-10MU ATtiny85V-10MUR ATtiny85-20PU ATtiny85-20SU ATtiny85-20SUR ATtiny85-20SH ATtiny85-20MU ATtiny85-20MUR 13 ...
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Packaging Information 7.1 8P3 Top View PLCS Side View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured ...
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Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs aren't included. 3. Determines the true geometric position. ...
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S8S1 Top View e Side View L End View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums,etc. 2325 Orchard Parkway San Jose, CA 95131 R ATtiny25/45/ ...
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Top View e Side View Note: These drawings are for general information only. Refer to JEDEC Drawing MO-153AC. 2325 Orchard Parkway San Jose, CA 95131 R 2586NS–AVR–04/ ...
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D 1 Pin TOP VIEW D2 Pin #1 Notch (0. BOTTOM VIEW Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5. Note: 2325 Orchard Parkway San Jose, CA 95131 R ATtiny25/45/85 18 ...
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Errata 8.1 Errata ATtiny25 The revision letter in this section refers to the revision of the ATtiny25 device. 8.1.1 Rev D and E No known errata. 8.1.2 Rev B and C • EEPROM read may fail at low supply ...
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Rev B and C • PLL not locking • EEPROM read from application code does not work in Lock Bit Mode 3 • EEPROM read may fail at low supply voltage / low clock frequency • Timer Counter 1 ...
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The EEPROM is read before entering power down. – VCC is 4.5 volts or higher. Problem fix / Workaround – When using external clock, avoid setting the clock pin as Output. – Do not read the EEPROM if power ...
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... Errata ATtiny85 The revision letter in this section refers to the revision of the ATtiny85 device. 8.3.1 Rev B and C No known errata. 8.3.2 Rev A • EEPROM read may fail at low supply voltage / low clock frequency 1. EEPROM read may fail at low supply voltage / low clock frequency Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in invalid data ...
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Datasheet Revision History 9.1 Rev. 2586N-04/11 1. Added: – Section 2. Updated: – Document template. – Removed “Preliminary” on front page. All devices now final and in production. – Section – Program example on – Section – – Section ...
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Bit syntax throughout the datasheet, e.g. from CS02:0 to CS0[2:0]. 9.4 Rev. 2586K-01/08 1. Updated Document Template. 2. Added Sections: – – – 3. Updated Sections: – – – – – – – – – – ...
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... ADTS[2:0]: ADC Auto Trigger Source” on page 142 “SPMCSR – Store Program Memory Control and Status Register” on page “Errata ATtiny25” on page 217 “Errata ATtiny45” on page 217 “Errata ATtiny85” on page 220 “ATtiny25” on page 209 “ATtiny45” on page 210 “ATtiny85” on page 211 “ ...
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Rev. 2586I-09/ ATtiny25/45/85 26 Updated “Bit 0” in “PRR ...
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Rev. 2586H-06/ 9.8 Rev. 2586G-05/ 10. 11. 9.9 Rev. 2586F-04/ 9.10 Rev. 2586E-03/ ...
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Rev. 2586D-02/ 9.12 Rev. 2586C-06/ 9.13 Rev. 2586B-05/ 9.14 Rev. 2586A-02/05 Initial revision. ATtiny25/45/85 28 ...
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ATtiny25/45/85 29 ...
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