ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 19
ATxmega128B1
Manufacturer Part Number
ATxmega128B1
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128B1
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
53
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
1
Uart
2
Segment Lcd
160
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
10
Input Capture Channels
10
Pwm Channels
10
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega128B1-AU
Manufacturer:
TI
Quantity:
90
Company:
Part Number:
ATxmega128B1-U
Manufacturer:
FUJITSU
Quantity:
632
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4. Memories
4.1
4.2
4.3
8291A–AVR–10/11
Features
Overview
Flash Program Memory
•
•
•
•
This section describes the different memory sections. The AVR architecture has two main mem-
ory spaces, the program memory and the data memory. Executable code can reside only in the
program memory, while data can be stored in the program memory and the data memory. The
data memory includes the internal SRAM and EEPROM for nonvolatile data storage. All memory
spaces are linear and require no memory bank switching. Nonvolatile memory (NVM) spaces
can be locked for further write and read/write operations. This prevents unrestricted access to
the application software.
A separate memory section contains the fuse bytes. These are used for configuring important
system functions, and can only be written by an external programmer.
All XMEGA devices contain on-chip in-system reprogrammable flash memory for program stor-
age. The flash memory can be accessed for read and write from an external programmer
through the PDI or from application software running in the device.
Flash program memory
Data memory
Production signature row memory for factory programmed data
User signature row
– One linear address space
– In-system programmable
– Self-programming and boot loader support
– Application section for application code
– Application table section for application code or data storage
– Boot section for application code or bootloader code
– Separate read/write protection lock bits for all sections
– Built in fast CRC check of a selectable flash program memory section
– One linear address space
– Single-cycle access from CPU
– SRAM
– EEPROM
– I/O memory
– Bus arbitration
– Separate buses for SRAM, EEPROM and I/O memory access
Byte and page accessible
Optional memory mapping for direct load and store
Configuration and status registers for all peripherals and modules
16 bit-accessible general purpose registers for global variables or flags
Safe and deterministic handling of priority between CPU, DMA controller, and other bus
masters
Simultaneous bus access for CPU and DMA controller
ID for each microcontroller device type
Serial number for each device
Calibration bytes for factory calibrated peripherals
One flash page in size
Can be read and written from software
Content is kept after chip erase
Atmel AVR XMEGA B
19
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