ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 273
ATxmega128B1
Manufacturer Part Number
ATxmega128B1
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128B1
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
53
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
1
Uart
2
Segment Lcd
160
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
10
Input Capture Channels
10
Pwm Channels
10
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega128B1-AU
Manufacturer:
TI
Quantity:
90
Company:
Part Number:
ATxmega128B1-U
Manufacturer:
FUJITSU
Quantity:
632
- Current page: 273 of 425
- Download datasheet (7Mb)
21.4
8291A–AVR–10/11
Frame Formats
Table 21-2.
The leading edge is the first clock edge of a clock cycle. The trailing edge is the last clock edge
of a clock cycle.
Figure 21-4. UCPHA and INVEN data transfer timing diagrams.
Data transfer is frame based, where a serial frame consists of one character of data bits with
synchronization bits (start and stop bits) and an optional parity bit for error checking. Note that
this does not apply to master SPI operation (See
USART accepts all combinations of the following as valid frame formats:
A frame starts with the start bit, followed by all the data bits (least-significant bit first and most-
significant bit last). If enabled, the parity bit is inserted after the data bits, before the first stop bit.
One frame can be directly followed by a start bit and a new frame, or the communication line can
return to the idle (high) state.
frame formats. Bits inside brackets are optional.
• 1 start bit
• 5, 6, 7, 8, or 9 data bits
• no, even, or odd parity bit
• 1 or 2 stop bits
SPI Mode
0
1
2
3
XCK
Data setup (TXD)
Data sample (RXD)
Data setup (TXD)
Data sample (RXD)
XCK
INVEN and UCPHA functionality.
INVEN
0
0
1
1
UCPOL=0
Figure 21-5 on page 274
UCPHA
0
1
0
1
Leading Edge
Rising, sample
Rising, setup
Falling, sample
Falling, setup
”SPI Frame Formats” on page
Atmel AVR XMEGA B
XCK
Data setup (TXD)
Data sample (RXD)
XCK
Data setup (TXD)
Data sample (RXD)
illustrates the possible combinations of
Trailing Edge
Falling, setup
Falling, sample
Rising, setup
Rising, sample
UCPOL=1
274). The
273
Related parts for ATxmega128B1
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
INTERVAL AND WIPE/WASH WIPER CONTROL IC WITH DELAY
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
Low-Voltage Voice-Switched IC for Hands-Free Operation
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
MONOLITHIC INTEGRATED FEATUREPHONE CIRCUIT
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
AM-FM Receiver IC U4255BM-M
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
Monolithic Integrated Feature Phone Circuit
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
Multistandard Video-IF and Quasi Parallel Sound Processing
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
High-performance EE PLD
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
8-bit Flash Microcontroller
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
2-Wire Serial EEPROM
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
U6046BREAR WINDOW HEATING TIMER / LONG-TERM TIMER
Manufacturer:
ATMEL Corporation
Datasheet: