ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 33
ATxmega128B1
Manufacturer Part Number
ATxmega128B1
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128B1
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
53
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
1
Uart
2
Segment Lcd
160
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
10
Input Capture Channels
10
Pwm Channels
10
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega128B1-AU
Manufacturer:
TI
Quantity:
90
Company:
Part Number:
ATxmega128B1-U
Manufacturer:
FUJITSU
Quantity:
632
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4.15.6
8291A–AVR–10/11
LOCKBITS – Lock Bit Register
• Bit 2:0 – BODLEVEL[2:0]: Brownout Detection Voltage Level
These fuse bits sets the BOD voltage level. Refer to
BOD level nominal values, see
• Bit 7:6 – BLBB[1:0]: Boot Lock Bit Boot Loader Section
These lock bits control the security level for the boot loader section. The BLBB bits can only be
written to a more strict locking. Resetting the BLBB bits is possible by executing a chip erase
command.
Table 4-9.
• Bit 5:4 – BLBA[1:0]: Boot Lock Bit Application Section
These lock bits control the security level for the application section. The BLBA bits can only be
written to a more strict locking. Resetting the BLBA bits is possible by executing a chip erase
command.
Bit
+0x07
Read/Write
Initial Value
BLBB[1:0]
11
10
01
00
Boot lock bit for the boot loader section.
R/W
7
1
BLBB[1:0]
Group Configuration
R/W
6
1
RWLOCK
NOLOCK
WLOCK
RLOCK
Table 9-2 on page
R/W
5
1
BLBA[1:0]
R/W
4
1
Description
No lock – no restrictions for SPM and (E)LPM accessing
the boot loader section.
Write lock – SPM is not allowed to write the boot loader
section.
Read lock – (E)LPM executing from the application
section is not allowed to read from the boot loader
section.
If the interrupt vectors are placed in the application
section, interrupts are disabled while executing from the
boot loader section.
Read and write lock – SPM is not allowed to write to the
boot loader section, and (E)LPM executing from the
application section is not allowed to read from the boot
loader section.
If the interrupt vectors are placed in the application
section, interrupts are disabled while executing from the
boot loader section.
108.
R/W
”Reset System” on page 105
3
1
BLBAT[1:0]
Atmel AVR XMEGA B
R/W
2
1
R/W
1
1
LB[1:0]
R/W
0
1
for details. For
LOCKBITS
33
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