M42800A Atmel Corporation, M42800A Datasheet - Page 16

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

7.8
8. Peripherals
8.0.1
8.0.2
16
External Bus Interface
AT91M42800A
Peripheral Registers
Peripheral Interrupt Control
The External Bus Interface handles the accesses between addresses 0x0040 0000 and
0xFFC0 0000. It generates the signals that control access to the external devices, and can be
configured from eight 1-Mbyte banks up to four 16-Mbyte banks. In all cases it supports byte,
half-word and word aligned accesses.
For each of these banks, the user can program:
The External Bus Interface features also the Early Read Protocol, configurable for all the
devices, that significantly reduces access time requirements on an external device.
The AT91M42800A peripherals are connected to the 32-bit wide Advanced Peripheral Bus.
Peripheral registers are only word accessible. Byte and half-word accesses are not supported.
If a byte or a half-word access is attempted, the memory controller automatically masks the
lowest address bits and generates a word access.
Each peripheral has a 16-Kbyte address space allocated (the AIC only has a 4-Kbyte address
space).
The following registers are common to all peripherals:
Unused bits in the peripheral registers are shown as “–” and must be written at 0 for upward
compatibility. These bits read 0.
The Interrupt Control of each peripheral is controlled from the status register using the inter-
rupt mask. The status register bits are ANDed to their corresponding interrupt mask bits and
• Number of wait states
• Number of data float times (wait time after the access is finished to prevent any bus
• Data bus width (8-bit or 16-bit)
• With a 16-bit wide data bus, the user can program the EBI to control one 16-bit device
• Control Register – Write-only register that triggers a command when a one is written to the
• Mode Register – read/write register that defines the configuration of the peripheral. Usually
• Data Registers – read and/or write register that enables the exchange of data between the
• Status Register – Read-only register that returns the status of the peripheral.
• Enable/Disable/Status Registers are shadow command registers. Writing a one in the
contention in case the device takes too long in releasing the bus)
(Byte Access Select mode) or two 8-bit devices in parallel that emulate a
16-bit memory (Byte Write Access mode).
corresponding position at the appropriate address. Writing a zero has no effect.
has a value of 0x0 after a reset.
processor and the peripheral.
Enable Register sets the corresponding bit in the Status Register. Writing a one in the
Disable Register resets the corresponding bit and the result can be read in the Status
Register. Writing a bit to zero has no effect. This register access method maximizes the
efficiency of bit manipulation, and enables modification of a register with a single non-
interruptible instruction, replacing the costly read-modify-write operation.
1779D–ATARM–14-Apr-06