SAM3N2A Atmel Corporation, SAM3N2A Datasheet - Page 143
SAM3N2A
Manufacturer Part Number
SAM3N2A
Description
Manufacturer
Atmel Corporation
Specifications of SAM3N2A
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
48 MHz
Cpu
Cortex-M3
# Of Touch Channels
23
Hardware Qtouch Acquisition
No
Max I/o Pins
47
Ext Interrupts
47
Quadrature Decoder Channels
2
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
2
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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10.18.6.1
10.18.6.2
10.18.6.3
10.18.6.4
10.18.6.5
11011A–ATARM–04-Oct-10
MRS
MRS
Syntax
Operation
Restrictions
Condition flags
Examples
R0, PRIMASK ; Read PRIMASK value and write it to R0
Move the contents of a special register to a general-purpose register.
where:
cond
Rd
spec_reg
PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL.
Use MRS in combination with MSR as part of a read-modify-write sequence for updating a PSR,
for example to clear the Q flag.
In process swap code, the programmers model state of the process being swapped out must be
saved, including relevant PSR contents. Similarly, the state of the process being swapped in
must also be restored. These operations use MRS in the state-saving instruction sequence and
MSR in the state-restoring instruction sequence.
BASEPRI_MAX is an alias of BASEPRI when used with the MRS instruction.
See
Rd must not be SP and must not be PC.
This instruction does not change the flags.
MRS{cond} Rd, spec_reg
“MSR” on page
is an optional condition code, see
is the destination register.
can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP,
144.
“Conditional execution” on page
84.
SAM3N
143
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