SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 32
SAM9XE512
Manufacturer Part Number
SAM9XE512
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9XE128.pdf
(860 pages)
4.SAM9XE128.pdf
(48 pages)
Specifications of SAM9XE512
Flash (kbytes)
512 Kbytes
Pin Count
217
Max. Operating Frequency
180 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
6
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.65 to 1.95
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9XE128 PDF datasheet #3
- SAM9XE128 PDF datasheet #4
- Current page: 32 of 248
- Download datasheet (2Mb)
Programmer’s Model
2.2.1
2.2.2
2-4
Addresses in an ARM926EJ-S system
Accessing CP15 registers
Domain
Address type
All CP15 register bits that are defined and contain state are set to 0 by Reset except:
•
•
•
Three distinct types of address exist in an ARM926EJ-S system. Table 2-2 shows the
address types in ARM926EJ-S processor.
This is an example of the address manipulation that occurs when the ARM9EJ-S core
requests an instruction:
1.
2.
3.
4.
You can only access CP15 registers with MRC and MCR instructions in a privileged
mode. The instruction bit pattern of the MCR and MRC instructions is shown in
Figure 2-1 on page 2-5.
Copyright © 2001-2003 ARM Limited. All rights reserved.
The V bit is set to 0 at reset if the VINITHI signal is LOW, or 1 if the VINITHI
signal is HIGH.
The B bit is set to 0 at reset if the BIGENDINIT signal is LOW, or 1 if the
BIGENDINIT signal is HIGH.
The instruction TCM is enabled at reset if the INITRAM pin is HIGH. This
enables booting from the instruction TCM and sets the ITCM bit in the ITCM
region register to 1.
The VA of the instruction is issued by the ARM9EJ-S core.
The VA is translated using the FCSE PID value to the MVA. The Instruction
Cache (ICache) and Memory Management Unit (MMU) detect the MVA (see
Process ID Register c13 on page 2-33).
If the protection check carried out by the MMU on the MVA does not abort and
the MVA tag is in the ICache, the instruction data is returned to the ARM9EJ-S
core.
If the protection check carried out by the MMU on the MVA does not abort, and
the cache misses (the MVA tag is not in the cache), then the MMU translates the
MVA to produce the PA. This address is given to the AMBA bus interface to
perform an external access.
ARM9EJ-S
Virtual Address (VA)
Caches and MMU
Modified Virtual Address (MVA)
Table 2-2 Address types in ARM926EJ-S
TCM and AMBA bus
Physical Address (PA)
ARM DDI0198D
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