AD7367 Analog Devices, AD7367 Datasheet - Page 7

• Manufacturer Part Number: AD7367
• Description: True Bipolar Input, Dual 14-Bit, 2-Channel, Simultaneous Sampling SAR ADC
• Manufacturer: Analog Devices

Specifications of AD7367

• Resolution (bits): 14bit
• # Chan: 4
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni,SE-Bip,SE-Uni
• Ain Range: Bip (Vref) x 2,Bip (Vref) x 4,Bip 10V,Bip 5.0V,Uni (Vref) x 4,Uni 10V
• Adc Architecture: SAR
• Pkg Type: SOP

TIMING SPECIFICATIONS
AV
unless otherwise noted.
Table 4.
Parameter
t
f
t
t
t
t
t
t
t
t
t
t
t
1
2
SCLK
CONVERT
QUIET
1
2
3
4
5
6
7
8
9
POWER-UP
Sample tested during initial release to ensure compliance. All input signals are specified with t
The time required for the output to cross is 0.4 V or 2.4 V.
All timing specifications are with a 25 pF load capacitance. With a load capacitance greater than 25 pF, a digital buffer or latch must be used. See the Terminology
section, Figure 25, and Figure 26.
2
CC
= DV
CC
2.7 V ≤ V
680
610
10
35
10
40
0
10
20
7
0.3 × t
0.3 × t
10
70
= 4.75 V to 5.25 V, V
30
SCLK
SCLK
DRIVE
1
< 4.75 V
Limit at T
DD
= 11.5 V to 16.5 V, V
MIN
4.75 V ≤ V
680
610
10
48
30
10
40
0
10
14
7
0.3 × t
0.3 × t
10
70
, T
MAX
SCLK
SCLK
DRIVE
≤ 5.25 V
SS
= −16.5 V to −11.5 V, V
Rev. D | Page 7 of 28
Unit
ns max
ns max
kHz min
MHz max
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
µs max
R
= t
Test Conditions/Comments
Conversion time, internal clock; CNVST falling edge to
BUSY falling edge
AD7367
AD7366
Frequency of serial read clock
Minimum quiet time required between the end of serial
read and the start of the next conversion
Minimum CNVST low pulse
CNVST falling edge to BUSY rising edge
BUSY falling edge to MSB, valid when CS is low for t
to BUSY going low
Delay from CS falling edge until Pin 1 (D
(D
Data access time after SCLK falling edge
SCLK to data valid hold time
SCLK low pulse width
SCLK high pulse width
CS rising edge to D
Power-up time from shutdown mode; time required
between CNVST rising edge and CNVST falling edge
F
OUT
= 5 ns (10% to 90% of V
DRIVE
B) are three-state disabled
= 2.7 V to 5.25 V, T
OUT
A, D
DRIVE
) and timed from a voltage level of 1.6 V.
OUT
A
B, high impedance
= −40°C to +85°C,
AD7366/AD7367
OUT
A) and Pin 23
4
prior