AD7793 Analog Devices, AD7793 Datasheet - Page 15

• Manufacturer Part Number: AD7793
• Description: 3-Channel, Low Noise, Low Power, 24-Bit Sigma Delta ADC with On-Chip In-Amp and Reference
• Manufacturer: Analog Devices

Specifications of AD7793

• Resolution (bits): 24bit
• # Chan: 3
• Sample Rate: n/a
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref/PGA Gain) p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: SOP

STATUS REGISTER
RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80 (AD7792)/0x88 (AD7793)
The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register,
select the next operation to be a read, and load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 13 outlines the bit designations for the status
register. SR0 through SR7 indicate the bit locations, and SR denotes that the bits are in the status register. SR7 denotes the first bit of the
data stream. The number in parentheses indicates the power-on/reset default status of that bit.
SR7
RDY(1)
Table 13. Status Register Bit Designations
Bit Location
SR7
SR6
SR5 to SR4
SR3
SR2 to SR0
MODE REGISTER
RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x000A
The mode register is a 16-bit register from which data can be read or to which data can be written. This register is used to select the
operating mode, update rate, and clock source. Table 14 outlines the bit designations for the mode register. MR0 through MR15 indicate
the bit locations, MR denoting the bits are in the mode register. MR15 denotes the first bit of the data stream. The number in parentheses
indicates the power-on/reset default status of that bit. Any write to the setup register resets the modulator and filter and sets the RDY bit.
MR15
MD2(0)
MR7
CLK1(0)
Table 14. Mode Register Bit Designations
Bit Location
MR15 to
MR13
MR12 to MR8
MR7 to MR6
MR5 to MR4
MR3 to MR0
Bit Name
MD2 to
MD0
0
CLK1 to
CLK0
0
FS3 to FS0
Bit Name
RDY
ERR
0
0/1
CH2 to CH0
MR14
MD1(0)
MR6
CLK0(0)
SR6
ERR(0)
Description
Mode Select Bits. These bits select the operational mode of the AD7792/AD7793 (see Table 15).
These bits must be programmed with a Logic 0 for correct operation.
These bits are used to select the clock source for the AD7792/AD7793. Either an on-chip 64 kHz clock can be
used, or an external clock can be used. The ability to override using an external clock allows several
AD7792/AD7793 devices to be synchronized. In addition, 50 Hz/60 Hz is improved when an accurate external
clock drives the AD7792/AD7793.
CLK1
0
0
1
1
These bits must be programmed with a Logic 0 for correct operation.
Filter Update Rate Select Bits (see Table 16).
Description
Ready Bit for ADC. Cleared when data is written to the ADC data register. The RDY bit is set automatically
after the ADC data register has been read or a period of time before the data register is updated with a new
conversion result to indicate to the user not to read the conversion data. It is also set when the part is
placed in power-down mode. The end of a conversion is indicated by the DOUT/RDY pin also. This pin can
be used as an alternative to the status register for monitoring the ADC for conversion data.
ADC Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written to
the ADC data register has been clamped to all 0s or all 1s. Error sources include overrange and underrange.
Cleared by a write operation to start a conversion.
These bits are automatically cleared.
This bit is automatically cleared on the AD7792 and is automatically set on the AD7793.
These bits indicate which channel is being converted by the ADC.
SR5
0(0)
MR13
MD0(0)
MR5
0(0)
CLK0
0
1
0
1
ADC Clock Source
Internal 64 kHz Clock. Internal clock is not available at the CLK pin.
Internal 64 kHz Clock. This clock is made available at the CLK pin.
External 64 kHz Clock Used. An external clock gives better 50 Hz/60 Hz rejection. See
specifications for external clock.
External Clock Used. The external clock is divided by 2 within the AD7792/AD7793.
SR4
0(0)
MR12
0(0)
MR4
0(0)
Rev. B | Page 15 of 32
SR3
0/1
MR11
0(0)
MR3
FS3(1)
SR2
CH2(0)
MR10
0(0)
MR2
FS2(0)
SR1
CH1(0)
MR9
0(0)
MR1
FS1(1)
AD7792/AD7793
SR0
CH0(0)
MR8
0(0)
MR0
FS0(0)