AD7793 Analog Devices, AD7793 Datasheet - Page 17

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AD7793

Manufacturer Part Number
AD7793
Description
3-Channel, Low Noise, Low Power, 24-Bit Sigma Delta ADC with On-Chip In-Amp and Reference
Manufacturer
Analog Devices
Datasheet

Specifications of AD7793

Resolution (bits)
24bit
# Chan
3
Sample Rate
n/a
Interface
Ser,SPI
Analog Input Type
Diff-Uni
Ain Range
(2Vref/PGA Gain) p-p
Adc Architecture
Sigma-Delta
Pkg Type
SOP

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FS3
1
1
1
1
1
1
1
CONFIGURATION REGISTER
RS2, RS1, RS0 = 0, 1, 0; Power-On/Reset = 0x0710
The configuration register is a 16-bit register from which data can be read or to which data can be written. This register is used to con-
figure the ADC for unipolar or bipolar mode, enable or disable the buffer, enable or disable the burnout currents, select the gain, and
select the analog input channel. Table 17 outlines the bit designations for the filter register. CON0 through CON15 indicate the bit
locations; CON denotes that the bits are in the configuration register. CON15 denotes the first bit of the data stream. The number in
parentheses indicates the power-on/reset default status of that bit.
CON15
VBIAS1(0)
CON7
REFSEL(0)
Table 17. Configuration Register Bit Designations
Bit Location
CON15 to
CON14
CON13
CON12
CON11
CON10 to
CON8
FS2
0
0
0
1
1
1
1
Bit Name
VBIAS1 to
VBIAS0
BO
U/B
BOOST
G2 to G0
FS1
0
1
1
0
0
1
1
CON14
VBIAS0(0)
CON6
0(0)
FS0
1
0
1
0
1
0
1
Description
Bias Voltage Generator Enable. The negative terminal of the analog inputs can be biased up to AV
bits are used in conjunction with the boost bit.
VBIAS1
0
0
1
1
Burnout Current Enable Bit. When this bit is set to 1 by the user, the 100 nA current sources in the signal path
are enabled. When BO = 0, the burnout currents are disabled. The burnout currents can be enabled only
when the buffer or in-amp is active.
Unipolar/Bipolar Bit. Set by user to enable unipolar coding; that is, zero differential input results in 0x000000
output, and a full-scale differential input results in 0xFFFFFF output. Cleared by the user to enable bipolar
coding. Negative full-scale differential input results in an output code of 0x000000, zero differential input
results in an output code of 0x800000, and a positive full-scale differential input results in an output code of
0xFFFFFF.
This bit is used in conjunction with the VBIAS1 and VBIAS0 bits. When set, the current consumed by the bias
voltage generator is increased. This reduces its power-up time.
Gain Select Bits.
Written by the user to select the ADC input range as follows:
G2
0
0
0
0
1
1
1
1
f
16.7
16.7
12.5
10
8.33
6.25
4.17
ADC
CON13
BO(0)
CON5
0(0)
G1
0
0
1
1
0
0
1
1
(Hz)
G0
0
1
0
1
0
1
0
1
t
120
120
160
200
240
320
480
SETTLE
CON12
U/B(0)
CON4
BUF(1)
VBIAS0
0
1
0
1
1 (In-amp not used)
2 (In-amp not used)
4
8
16
32
64
128
Gain
Rev. B | Page 17 of 32
(ms)
CON11
BOOST(0)
CON3
0(0)
Rejection @ 50 Hz/60 Hz (Internal Clock)
80 dB (50 Hz only)
65 dB (50 Hz and 60 Hz)
66 dB (50 Hz and 60 Hz)
69 dB (50 Hz and 60 Hz)
70 dB (50 Hz and 60 Hz)
72 dB (50 Hz and 60 Hz)
74 dB (50 Hz and 60 Hz)
Bias Voltage
Bias voltage generator disabled
Bias voltage connected to AIN1(−)
Bias voltage connected to AIN2(−)
Reserved
ADC Input Range (2.5 V Reference)
2.5 V
1.25 V
625 mV
312.5 mV
156.2 mV
78.125 mV
39.06 mV
19.53 mV
CON10
G2(1)
CON2
CH2(0)
CON9
G1(1)
CON1
CH1(0)
AD7792/AD7793
CON8
G0(1)
CON0
CH0(0)
DD
/2. These

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