AD7791 Analog Devices, AD7791 Datasheet
AD7791
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AD7791 Summary of contents
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... AD7791 GND Figure 1. GENERAL DESCRIPTION The AD7791 is a low power, complete analog front end for low frequency measurement applications. It contains a low noise 24-bit ∑-∆ ADC with one differential input that can be buffered or unbuffered. The device operates from an internal clock. Therefore, the user does not have to supply a clock source to the device ...
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... AD7791 TABLE OF CONTENTS AD7791—Specifications.................................................................. 3 Timing Characteristics..................................................................... 5 Absolute Maximum Ratings............................................................ 7 Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ............................................. 9 On-Chip Registers .......................................................................... 10 Communications Register (RS1, RS0 = 0, 0) ......................................................................... 10 Status Register (RS1, RS0 = 0, 0; Power-on/Reset = 0x8C).............................. 11 Mode Register (RS1, RS0 = 0, 1; Power-on/Reset = 0x02)............................... 11 Filter Register (RS1, RS0 = 1, 0 ...
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... Input current varies with input voltage typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[2:0] = 100 typ, 50 ± 1 Hz, FS[2:0] = 101 typ, 60 ± 1 Hz, FS[2:0] = 011 AIN = 100 dB typ, FS[2:0] = 100 4 50 ± (FS[2:0] = 101 ), 60 ± (FS[2:0] = 011 REFIN = REFIN(+) – REFIN(– V). DD AD7791 ...
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... I Current DD I (Power-Down Mode Digital inputs equal GND The current consumption can be further reduced by using the ADC in one of the low power modes (see Table 14). 1 AD7791B Unit 65 dB min 80 dB min 80 dB min 100 dB typ 110 dB typ 0.8 V max ...
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... SCLK Inactive Edge to DOUT/RDY High CS Falling Edge to SCLK Active Edge Setup Time Data Valid to SCLK Edge Setup Time Data Valid to SCLK Edge Hold Time CS Rising Edge to SCLK Edge Hold Time = (10 and timed from a voltage level of 1 limits AD7791 4 4 ...
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... AD7791 DOUT/RDY (O) I (1.6mA WITH V SINK 100µA WITH V TO OUTPUT 1.6V PIN 50pF I (200µA WITH V SOURCE 100µA WITH V Figure 2. Load Circuit for Timing Characterization CS ( MSB SCLK ( INPUT OUTPUT Figure 3. Read Cycle Timing Diagram ...
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... Exposure to absolute –0 0.3 V maximum rating conditions for extended periods may affect DD –0 0.3 V device reliability. DD –40°C to +105°C –65°C to +150°C 150°C 206°C/W 44°C/W 300°C 220°C Rev Page AD7791 ...
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... AD7791 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SCLK AD7791 AIN(+) 3 TOP VIEW 8 (Not to Scale) AIN(– REF(+) 5 6 04227-0-005 Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Function 1 SCLK Serial Clock Input for Data Transfers to and from the ADC. The SCLK has a Schmitt- triggered input, making the interface suitable for opto-isolated applications ...
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... RMS NOISE = 1.25µ READ NO. Figure 10. Noise Plot in Clock Divide by 8 Mode (CDIV0 = CDIV1 = UPDATE RATE = 16.6Hz T = 25° 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 V (V) REF Figure 11. RMS Noise vs. Reference Voltage AD7791 8388616 04227-0-014 100 04227-0-013 4.5 5.0 04227-0-015 ...
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... AD7791 ON-CHIP REGISTERS The ADC is controlled and configured via a number of on-chip registers, which are described on the following pages. In the following descriptions, set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise stated. COMMUNICATIONS REGISTER (RS1, RS0 = 0, 0) The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the com- munications register ...
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... SR3 1 This bit is automatically set. SR2 1 This bit is automatically set if the device is an AD7791. It can be used to distinguish between the AD7791 and AD7790, in which the bit is cleared. SR1–SR0 CH1–CH0 These bits indicate which channel is being converted by the ADC. MODE REGISTER (RS1, RS0 = 0, 1; POWER-ON/RESET = 0x02) The mode register is an 8-bit register from which data can be read or to which data can be written ...
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... These bits must be programmed with a Logic 0 for correct operation. FR5–FR4 CLKDIV1– These bits are used to operate the AD7791 in the lower power modes. The clock is internally divided and CDIV0 the power is reduced. In the low power modes, the update rates will scale with the clock frequency so that dividing the clock by 2 causes the update rate to be reduced by a factor of 2 also ...
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... The conversion result from the ADC is stored in this data register. This is a read-only register. On completion of a read operation from this register, the RDY bit/pin is set. (Hz) f3dB (Hz) RMS Noise (µV) ADC 3.36 4.7 1.6 4 1.5 4 1.5 3.2 1.2 2.3 1.1 Rev Page AD7791 Rejection Hz/60 Hz (Default Setting 50/60 Hz ...
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... When the internal clock is reduced, the update rate will also be reduced. For example, if the filter bits are set to give an update rate of 16.6 Hz when the AD7791 is operated in full power mode, the update rate will equal 8 divide by 2 mode. In the low power modes, there may be some degradation in the ADC performance. Typ Current, Unbuffered (µ ...
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... The serial interface can be reset by writing a series the DIN input Logic 1 is written to the AD7791 line for at least 32 serial clock cycles, the serial interface is reset. This ensures that in 3-wire systems, the interface can be reset to a known state if the interface gets lost due to a software error or some glitch in the system ...
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... DOUT/RDY SCLK Continuous Conversion Mode This is the default power-up mode. The AD7791 will continu- ously convert, the RDY pin in the status register going low each time a conversion is complete low, the DOUT/ RDY line will also go low when a conversion is complete. To read a con- version, the user can write to the communications register, indicating that the next operation is a read of the data register ...
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... If the user has not read the conversion before the completion of the next conversion or if insufficient serial clocks are applied to the AD7791 to read the word, the serial output register is reset when the next conver- sion is complete and the new conversion is placed in the output serial register ...
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... GND. BIPOLAR/UNIPOLAR CONFIGURATION The analog input to the AD7791 can accept either unipolar or bipolar input voltage ranges. A bipolar input range does not imply that the part can tolerate negative voltages with respect to system GND. Unipolar and bipolar signals on the AIN(+) input are referenced to the voltage on the AIN(– ...
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... The AD7791’s ground plane should be allowed to run under the AD7791 to prevent noise coupling. The power supply lines to the AD7791 should use as wide a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should ...
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... Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Table 16. Ordering Guide Model Temperature Range AD7791BRM –40°C to +105°C AD7791BRM-REEL –40°C to +105°C © 2003 Analog Devices, Inc. All rights reserved. Trademarks and regis- tered trademarks are the property of their respective companies. 3.00 BSC ...