ADM1169 Analog Devices, ADM1169 Datasheet - Page 6

• Manufacturer Part Number: ADM1169
• Description: Super Sequencer and Monitor with Margining Control and Non-Volatile Fault Recording
• Manufacturer: Analog Devices

Specifications of ADM1169

• # Supplies Monitored: 8
• Volt Monitoring Accuracy: 1%
• # Output Drivers: 8
• Fet Drive/enable Output: Both
• Voltage Readback: 12-bit ADC
• Supply Adj/margining: 12-bit ADC+4 DACs
• Package: 32 ld LQFP,40 ld LFCSP

ADM1169
Parameter
PROGRAMMABLE DRIVER OUTPUTS
DIGITAL INPUTS (VXx, A0, A1)
SERIAL BUS DIGITAL INPUTS (SDA, SCL)
SERIAL BUS TIMING
SEQUENCING ENGINE TIMING
1
2
At least one of the VH, VPx pins must be ≥3.0 V to maintain the device supply on VDDCAP.
Specification is not production tested but is supported by characterization data at initial product release.
High Voltage (Charge Pump) Mode
Standard (Digital Output) Mode (PDO1 to PDO8)
Three-State Output Leakage Current
Oscillator Frequency
Input High Voltage, V
Input Low Voltage, V
Input High Current, I
Input Low Current, I
Input Capacitance
Programmable Pull-Down Current, I
Input High Voltage, V
Input Low Voltage, V
Output Low Voltage, V
Clock Frequency, f
Bus Free Time, t
Start Setup Time, t
Stop Setup Time, t
Start Hold Time, t
SCL Low Time, t
SCL High Time, t
SCL, SDA Rise Time, t
SCL, SDA Fall Time, t
Data Setup Time, t
Data Hold Time, t
Input Low Current, I
State Change Time
(PDO1 to PDO6)
Output Impedance
V
I
V
V
I
I
R
I
OUTAVG
OL
SINK
SOURCE
OH
OH
OL
PULL-UP
2
2
(VPx)
2
BUF
LOW
HIGH
HD;STA
HD;DAT
SCLK
SU;STO
SU;DAT
SU;STA
IL
IL
F
IL
IH
IL
R
IH
IH
OL
2
PULL-DOWN
Min
11
10.5
2.4
V
0
16
90
2.0
−1
2.0
1.3
0.6
0.6
0.6
1.3
0.6
100
250
PU
− 0.3
Rev. 0 | Page 6 of 36
Typ
500
12.5
12
20
20
100
5
20
10
Max
4.5
0.50
60
29
2
110
0.8
1
0.8
0.4
400
300
300
1
14
13.5
20
10
Unit
kΩ
V
V
μA
V
V
V
V
mA
mA
kΩ
mA
μA
kHz
V
V
μA
μA
pF
μA
V
V
V
kHz
μs
μs
μs
μs
μs
μs
ns
ns
ns
ns
μA
μs
Test Conditions/Comments
I
I
2 V < V
V
V
V
I
Maximum sink current per PDOx pin
Maximum total sink for all PDOx pins
Internal pull-up
Current load on any VPx pull-ups, that is, total
source current available through any number of
PDO pull-up switches configured onto any one
VPx pin
V
All on-chip time delays derived from this clock
Maximum V
Maximum V
V
V
VDDCAP = 4.75 V, T
is required
I
See Figure 38
V
OH
OH
OL
OUT
PU
PU
PU
PDO
IN
IN
IN
= 20 mA
= 0 μA
= 1 μA
= 5.5 V
= 0 V
= 0 V
(pull-up to VDDCAP or VPx) = 2.7 V, I
to VPx = 6.0 V, I
≤ 2.7 V, I
= −3.0 mA
= 14.4 V
OH
< 7 V
OH
IN
IN
= 5.5 V
= 5.5 V
= 0.5 mA
OH
A
= 25°C, if known logic state
= 0 mA
OH
= 0.5 mA