ADUC7126 Analog Devices, ADUC7126 Datasheet - Page 37

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ADUC7126

Manufacturer Part Number
ADUC7126
Description
Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler
Manufacturer
Analog Devices
Datasheet

Specifications of ADUC7126

Mcu Core
ARM7 TDMI
Mcu Speed (mips)
40
Gpio Pins
40
Adc # Channels
16
Other
PWM

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ADC CIRCUIT OVERVIEW
The analog-to-digital converter is a fast, multichannel, 12-bit
ADC. It can operate from 2.7 V to 3.6 V supplies and is capable
of providing a throughput of up to 1 MSPS when the clock source
is 41.78 MHz. This block provides the user with a multichannel
multiplexer, a differential track-and-hold, an on-chip reference,
and an ADC.
The ADC consists of a 12-bit successive approximation con-
verter based around two capacitor DACs. Depending on the
input signal configuration, the ADC can operate in one of
three different modes.
The converter accepts an analog input range of 0 V to V
operating in single-ended or pseudo differential mode. In fully
differential mode, the input signal must be balanced around a
common-mode voltage (V
maximum amplitude of 2 × V
A high precision, low drift, factory calibrated, 2.5 V reference is
provided on chip. An external reference can also be connected as
described in the Band Gap Reference section.
Single or continuous conversion modes can be initiated in the
software. An external CONV
the on-chip PLA, or a Timer0 or Timer1 overflow can also be
used to generate a repetitive trigger for ADC conversions.
A voltage output from an on-chip band gap reference propor-
tional to absolute temperature can also be routed through the
front-end ADC multiplexer, effectively an additional ADC channel
input. This facilitates an internal temperature sensor channel
that measures die temperature.
TRANSFER FUNCTION
Pseudo Differential and Single-Ended Modes
In pseudo differential or single-ended mode, the input range is
0 V to V
differential and single-ended modes with
Figure 27. Examples of Balanced Signals in Fully Differential Mode
Fully differential mode, for small and balanced signals
Single-ended mode, for any single-ended signals
Pseudo differential mode, for any single-ended signals,
taking advantage of the common-mode rejection offered
by the pseudo differential input
1 LSB = Full-Scale/4096, or
2.5 V/4096 = 0.61 mV, or
610 µV when V
REF
AV
. The output coding is straight binary in pseudo
V
CM
DD
0
REF
= 2.5 V
V
CM
CM
) in the 0 V to AV
START
REF
2V
V
CM
REF
(see Figure 27).
pin, an output generated from
2V
REF
DD
2V
range with a
REF
REF
when
Rev. B | Page 37 of 104
The ideal code transitions occur midway between successive
integer LSB values (that is, ½ LSB, 3 ⁄2 LSB, 5⁄2 LSB, … ,
FS − 3/2 LSB). The ideal input/output transfer characteristic
is shown in Figure 28.
Fully Differential Mode
The amplitude of the differential signal is the difference between
the signals applied to the V
V
the ADCCN register. The maximum amplitude of the differential
signal is, therefore, –V
regardless of the common mode (CM). The common mode is
the average of the two signals, for example, (V
is, therefore, the voltage that the two inputs are centered on.
This results in the span of each input being CM ± V
voltage must be set up externally, and its range varies with V
(see the Driving the Analog Inputs section).
The output coding is twos complement in fully differential mode
with 1 LSB = 2 × V
V
one to the right. This allows the result in ADCDAT to be declared
as a signed integer when writing C code. The designed code
transitions occur midway between successive integer LSB values
(that is, ½ LSB, 3⁄2 LSB, 5⁄2 LSB, … , FS − 3⁄2 LSB). The ideal
input/output transfer characteristic is shown in Figure 29.
Figure 28. ADC Transfer Function in Pseudo Differential or Single-Ended Mode
IN+
REF
SIGN
BIT
0 1111 1111 1110
0 1111 1111 1100
0 1111 1111 1010
0 0000 0000 0010
0 0000 0000 0000
1 1111 1111 1110
1 0000 0000 0100
1 0000 0000 0010
1 0000 0000 0000
is selected by the ADCCP register, and V
= 2.5 V. The output result is ±11 bits, but this is shifted by
1111 1111 1111
1111 1111 1110
1111 1111 1101
1111 1111 1100
0000 0000 0011
0000 0000 0010
0000 0000 0001
0000 0000 0000
Figure 29. ADC Transfer Function in Differential Mode
0V
–V
REF
REF
1LSB
1LSB =
/4096, or 2 × 2.5 V/4096 = 1.22 mV when
REF
1LSB =
+ 1LSB
to +V
IN+
2 × V
VOLTAGE INPUT (V
SCALE
4096
FULL-
4096
ADuC7124/ADuC7126
and V
REF
REF
VOLTAGE INPUT
p-p (that is, 2 × V
0LSB
IN–
pins (that is, V
IN
+ – V
IN−
IN+
IN
+V
+FS – 1LSB
is selected by
+ V
–)
REF
REF
REF
IN–
– 1LSB
IN+
/2. This
). This is
)/2, and
– V
REF
IN–
).

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