ADUC7126 Analog Devices, ADUC7126 Datasheet - Page 58

• Manufacturer Part Number: ADUC7126
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler
• Manufacturer: Analog Devices

Specifications of ADUC7126

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Gpio Pins: 40
• Adc # Channels: 16
• Other: PWM

ADuC7124/ADuC7126
DIGITAL PERIPHERAL
GENERAL-PURPOSE INPUT/OUTPUT
The ADuC7124/ADuC7126 provide 40 general-purpose, bidirec-
tional I/O (GPIO) pins. All I/O pins are 5 V tolerant, meaning
the GPIOs support an input voltage of 5 V.
In general, many of the GPIO pins have multiple functions (see
the Pin Configurations and Function Descriptions section for
pin function definitions). By default, the GPIO pins are configured
in GPIO mode.
All GPIO pins have an internal pull-up resistor (of about 100 kΩ),
and their drive capability is 1.6 mA. Note that a maximum of
20 GPIOs can drive 1.6 mA at the same time. Using the GPxPAR
registers, it is possible to enable/disable the pull-up resistors for
the following ports: P0.0, P0.4, P0.5, P0.6, P0.7, and the eight
GPIOs of P1.
The 40 GPIOs are grouped in five ports, Port 0 to Port 4 (Port x).
Each port is controlled by four or five MMRs.
Note that the kernel changes P0.6 from its default configuration
at reset (MRST) to GPIO mode. If MRST is used for external
circuitry, an external pull-up resistor should be used to ensure
that the level on P0.6 does not drop when the kernel switches
mode. Otherwise, P0.6 goes low for the reset period. For example,
if MRST is required for power-down, it can be reconfigured in
GP0CON MMR.
The input level of any GPIO can be read at any time in the
GPxDAT MMR, even when the pin is configured in a mode
other than GPIO. The PLA input is always active.
When the ADuC7124/ADuC7126 enter a power-saving mode,
the GPIO pins retain their state. Also, note that, by setting
RSTCFG Bit 0, the GPIO pins can retain their state during a
watchdog or software reset.
Rev. B | Page 58 of 104
Table 78. GPIO Pin Function Descriptions
Port
0
1
2
3
4
1
2
3
4
These pins should not be used by user code .
When configured in Mode 1, P0.7 is ECLK by default, or core clock output. To
See Table 90 for SPM configurations.
The CONV
configure it as a clock input, the MDCLK bits in PLLCON must be set to 11.
Pin
BM/P0.0
TDI/P0.1
TDO/P0.2
TRST/P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
START
signal is active in all modes of P2.0.
1
1
1
00
GPIO
GPIO/JTAG
GPIO/JTAG
GPIO/JTAG
GPIO/IRQ0
GPIO/IRQ1
GPIO
GPIO
GPIO/T1
GPIO
GPIO
GPIO
GPIO/IRQ2
GPIO/IRQ3
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO/RTCK
GPIO
GPIO
01
CMP
PWM4
PWM5
TRST
PWM
ADC
MRST
ECLK/XCLK
SIN0
SOUT0
RTS
CTS
RI
DCD
DSR
DTR
CONV
PWM0
PWM1
PWM0
PWM1
PWM2
PWM3
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM
PWM
SIN1
SOUT1
3
Configuration
3
3
3
3
BUSY
3
TRIP
TRIP
SYNC
START
4
2
10
MS0
BLE
BHE
A16
MS1
MS2
MS3
SIN0
SCL0
SDA0
SCL1
SDA1
CLK
MISO
MOSI
CSL
SOUT0
WS
RS
AE
MS0
MS1
MS2
MS3
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
3
3
3
3
3
3
3
3
11
PLAI[7]
ADC
PLAO[1]
PLAO[2]
PLAO[3]
PLAO[4]
PLAI[0]
PLAI[1]
PLAI[2]
PLAI[3]
PLAI[4]
PLAI[5]
PLAI[6]
PLAO[0]
PLAO[5]
PLAO[6]
PLAO[7]
SIN1
SOUT1
PLAI[8]
PLAI[9]
PLAI[10]
PLAI[11]
PLAI[12]
PLAI[13]
PLAI[14]
PLAI[15]
PLAO[8]
PLAO[9]
PLAO[10]
PLAO[11]
PLAO[12]
PLAO[13]
PLAO[14]
PLAO[15]
BUSY