ADUC7126 Analog Devices, ADUC7126 Datasheet - Page 60

no-image

ADUC7126

Manufacturer Part Number
ADUC7126
Description
Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler
Manufacturer
Analog Devices
Datasheet

Specifications of ADUC7126

Mcu Core
ARM7 TDMI
Mcu Speed (mips)
40
Gpio Pins
40
Adc # Channels
16
Other
PWM

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADUC7126BSTZ126
Manufacturer:
Analog Devices Inc
Quantity:
135
Part Number:
ADUC7126BSTZ126
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
ADUC7126BSTZ126-RL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
ADUC7126BSTZ126I
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
ADUC7126BSTZ126I
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
ADUC7126BSTZ126IRL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
ADuC7124/ADuC7126
The drive strength bits can be written only once after reset.
Additional writing to related bits has no effect on drive strength.
The GPIO drive strength and pull-up disable are not always
adjustable for GPIO port. Some control bits cannot be changed.
See Table 78 for details.
Table 84. GPxDAT Registers
Name
GP0DAT
GP1DAT
GP2DAT
GP3DAT
GP4DAT
The GPxDAT are Port x configuration and data registers. They
configure the direction of the GPIO pins of Port x, set the
output value for the pins configured as output, and store the
input value of the pins configured as input.
Table 85. GPxDAT MMR Bit Descriptions
Bit
[31:24]
[23:16]
[15:8]
[7:0]
Table 86. GPxSET Registers
Name
GP0SET
GP1SET
GP2SET
GP3SET
GP4SET
The GPxSET are data set Port x registers.
Table 87. GPxSET MMR Bit Descriptions
Bit
[31:24]
[23:16]
[15:0]
Table 88. GPxCLR Registers
Name
GP0CLR
GP1CLR
GP2CLR
GP3CLR
GP4CLR
The GPxCLR are data clear Port x registers.
Description
Reserved.
Data Port x set bit.
Set to 1 by the user to set a bit on Port x; also sets the
corresponding bit in the GPxDAT MMR.
Cleared to 0 by the user; does not affect the data output.
Reserved.
Description
Direction of the data.
Set to 1 by the user to configure the GPIO pin as
an output.
Cleared to 0 by the user to configure the GPIO pin
as an input.
Port x data output.
Reflect the state of Port x pins at reset (read only).
Port x data input (read only).
Address
0xFFFFF420
0xFFFFF430
0xFFFFF440
0xFFFFF450
0xFFFFF460
Address
0xFFFFF424
0xFFFFF434
0xFFFFF444
0xFFFFF454
0xFFFFF464
Address
0xFFFFF428
0xFFFFF438
0xFFFFF448
0xFFFFF458
0xFFFFF468
Default Value
0x000000XX
0x000000XX
0x000000XX
0x000000XX
0x000000XX
Default Value
0x000000XX
0x000000XX
0x000000XX
0x000000XX
0x000000XX
Default Value
0x000000XX
0x000000XX
0x000000XX
0x000000XX
0x000000XX
Access
R/W
R/W
R/W
R/W
R/W
Access
W
W
W
W
W
Access
W
W
W
W
W
Rev. B | Page 60 of 104
Table 89. GPxCLR MMR Bit Descriptions
Bit
[31:24]
[23:16]
[15:0]
SERIAL PORT MUX
The serial port mux multiplexes the serial port peripherals
(an SPI, UART, and two I
(PLA) to a set of 10 GPIO pins. Each pin must be configured to
one of its specific I/O functions as described in Table 90.
Table 90. SPM Configuration
SPM
SPM0
SPM1
SPM2
SPM3
SPM4
SPM5
SPM6
SPM7
SPM8
SPM9
SPM10
SPM11
SPM12
SPM13
Table 90 also details the mode for each of the SPMMUX pins.
This configuration has to be done via the GP0CON, GP1CON,
and GP2CON MMRs. By default, these 10 pins are configured
as GPIOs.
UART SERIAL INTERFACE
The UART peripheral is a full-duplex, universal, asynchronous
receiver/transmitter. The UART performs serial-to-parallel conver-
sions on data characters received from a peripheral device and
parallel-to-serial conversions on data characters received from
the CPU. The ADuC7124/ADuC7126 has been equipped with
two industry standard 16,450 type UARTs (UART0 and UART1).
Each UART features a fractional divider that facilitates high accu-
racy baud rate generation and is equipped with a 16-byte FIFO
for the transmitter and a 16-byte FIFO for the receiver. Both
UARTs can be configured as FIFO mode and non-FIFO mode.
The serial communication adopts an asynchronous protocol,
which supports various word lengths, stop bits, and parity
generation options selectable in the configuration register.
Description
Reserved.
Data Port x clear bit.
Set to 1 by the user to clear a bit on Port x; also clears
the corresponding bit in the GPxDAT MMR.
Cleared to 0 by the user; does not affect the data out.
Reserved.
GPIO
(00)
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P0.7
P2.0
P4.0
P4.1
P2.3
P2.4
UART
(01)
SIN0
SOUT0
RTS
CTS
RI
DCD
DSR
DTR
ECLK/XCLK
CONV
SIN1
SOUT1
N/A
PWM0
2
Cs) and the programmable logic array
START
UART/I
(10)
I2C0SCL
I2C0SDA
I2C1SCL
I2C1SDA
SPICLK
SPIMISO
SPIMOSI
SPI CS
SIN0
SOUT0
AD8
AD9
AE
MSO
2
C/SPI
PLA
(11)
PLAI[0]
PLAI[1]
PLAI[2]
PLAI[3]
PLAI[4]
PLAI[5]
PLAI[6]
PLAO[0]
PLAO[4]
PLAO[5]
PLAO[8]
PLAO[9]
SIN1
SOUT1

Related parts for ADUC7126