ADAV4622 Analog Devices, ADAV4622 Datasheet - Page 22

• Manufacturer Part Number: ADAV4622
• Description: Audio Processor for Advanced TV with Sound IF Demodulator and Stereo Decoder
• Manufacturer: Analog Devices

Specifications of ADAV4622

• Instructions/cycles: 2560
• Dac Dnr (db): 94dB
• Dac Thd+n: 86dB
• Product Description: Audio Processor for Advanced TV with Sound IF Demodulator and Stereo Decoder

ADAV4622
I
The ADAV4622 supports a 2-wire serial (I
microprocessor bus driving multiple peripherals. The
ADAV4622 is controlled by an external I
such as a microcontroller. The ADAV4622 is in slave mode
on the I
is self-booting, it becomes the master, and the EEPROM, which
contains the ROMs to be booted, is the slave. When the self-
boot process is complete, the ADAV4622 reverts to slave mode
on the I
the ADAV4622 is self-booting (refer to the Application Layer
section and the Loading a Custom Audio Processing Flow
section).
Initially, all devices on the I
the devices monitor the SDA and SCL lines for a start condition
and the proper address. The I
by establishing a start condition, defined by a high-to-low
transition on SDA while SCL remains high. This indicates that
an address/data stream follows. All devices on the bus respond
to the start condition and read the next byte (7-bit address plus
the R/ W bit) MSB first. The device that recognizes the transmit-
ted address responds by pulling the data line low during the
ninth clock pulse. This ninth bit is known as an acknowledge
bit. All other devices on the bus revert to an idle condition. The
R/ W bit determines the direction of the data. A Logic Level 0
on the LSB of the first byte means the master writes information
to the peripheral. A Logic Level 1 on the LSB of the first byte
means the master reads information from the peripheral. A data
transfer takes place until a stop condition is encountered. A stop
condition occurs when SDA transitions from low to high while
SCL is held high.
The ADAV4622 determines its I
the SDO0 pin after reset. Internally, the SDO0 pin is sampled by
four MCLKI edges to determine the state of the pin (high or
low). Because the pin has an internal pull-down resistor default,
the address of the ADAV4622 is 0x34 (write) and 0x35 (read).
An alternate address, 0x36 (write) and 0x37 (read), is available
by tying the SDO0 pin to ODVDD via a 10 kΩ resistor. The I
interface supports a clock frequency up to 400 kHz.
ADC INPUTS
The ADAV4622 has four ADC inputs. By default, these are
configured as two stereo inputs; however, because the audio
processor is programmable, these inputs can be reconfigured.
The ADC inputs are shown in Figure 23. The analog inputs are
current inputs (100 μA rms FS) with a 1.5 V dc bias voltage.
Any input voltage can be accommodated by choosing a suitable
combination of input resistor (R
using the formulas
2
C INTERFACE
R
R
IN
ISET
2
2
C bus, except during self-boot. While the ADAV4622
C bus. No other devices should access the I
= V
= 2R
FS rms
IN
/100 μA rms
/V
IN
2
C bus are in an idle state, wherein
2
C master initiates a data transfer
2
IN
C device address by sampling
) and ISET resistor (R
2
C master device,
2
C compatible)
2
C bus while
ISET
)
Rev. B | Page 22 of 28
2
C
Resistor matching (typically 1%) between R
important to ensure a full-scale signal on the ADC without
clipping.
ANALOG INPUT
ANALOG INPUT
ANALOG INPUT
ANALOG INPUT
I
The ADAV4622 has four I
default, synchronous to the master clock. Also available are two
SRCs capable of supporting any nonsynchronous input with a
sample rate between 5 kHz and 50 kHz. Any of the serial digital
inputs can be redirected through the SRC. Figure 24 shows a
block diagram of the input serial port.
LRCLK0
LRCLK1
LRCLK2
LRCLK0
LRCLK1
LRCLK2
2
BCLK0
BCLK1
BCLK2
BCLK0
BCLK1
BCLK2
S DIGITAL AUDIO INPUTS
SDIN0
SDIN1
SDIN2
SDIN3
SDIN0
SDIN1
SDIN2
SDIN3
SDIN0
SDIN1
SDIN2
SDIN3
FULL SCALE
FULL SCALE
FULL SCALE
FULL SCALE
100µA rms
100µA rms
100µA rms
100µA rms
R
20kΩ
ISET
AUXIN1R
AUXIN2R
AUXIN1L
AUXIN2L
20kΩ
20kΩ
20kΩ
20kΩ
LRCLK0
LRCLK1
LRCLK2
ISET
BCLK0
BCLK1
BCLK2
Figure 23. Analog Input Section
Figure 24. Digital Input Section
DC BIAS
DC BIAS
DC BIAS
DC BIAS
2
SRC1
SRC2
S digital audio inputs that are, by
1.5V
1.5V
1.5V
1.5V
SRC2B
SRC2C
SRC2A
SRC2B
SRC2C
IN
and R
ADC
ADC
ADC
ADC
PROCESSOR
24-BIT
24-BIT
24-BIT
24-BIT
ISET
AUDIO
is