SA58635 NXP Semiconductors, SA58635 Datasheet - Page 8

• Manufacturer Part Number: SA58635
• Manufacturer: NXP Semiconductors

NXP Semiconductors
8. Characteristics of the I
SA58635_1
Product data sheet
8.1.1 START and STOP conditions
7.5 Power-on reset
8.1 Bit transfer
When power is applied to AVDD, an internal power-on reset holds the SA58635 in a reset
condition until AVDD has reached V
the SA58635 registers and I
(all zeroes) causing all the channels to be deselected. Thereafter, AVDD must be lowered
below 0.2 V to reset the device.
The I
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see
Fig 4.
Fig 5.
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two
SDA
SCL
Bit transfer
Definition of START and STOP conditions
START condition
2
SDA
SCL
Figure
C-bus
S
Rev. 01 — 26 March 2010
5).
2
C-bus state machine are initialized to their default states
data valid
data line
stable;
POR
. At this point, the reset condition is released and
Figure
2 × 25 mW class-G stereo headphone driver
allowed
change
of data
4).
STOP condition
mba607
P
SA58635
© NXP B.V. 2010. All rights reserved.
mba608
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