LH75401_LH75411_N NXP Semiconductors, LH75401_LH75411_N Datasheet - Page 39

The NXP BlueStreak LH75401/LH75411 family consists of two low-cost 16/32-bit System-on-Chip (SoC) devices

LH75401_LH75411_N

Manufacturer Part Number
LH75401_LH75411_N
Description
The NXP BlueStreak LH75401/LH75411 family consists of two low-cost 16/32-bit System-on-Chip (SoC) devices
Manufacturer
NXP Semiconductors
Datasheet
System-on-Chip
POWER SUPPLY SEQUENCING
internal 1.8 V regulator), the external 1.8 V power sup-
ply must be energized before the 3.3 V supply. Other-
wise, the 1.8 V supply may not lag the 3.3 V supply by
more than 10 µs.
ence between the two power supplies must be within
1.5 V during power supply ramp up.
should be applied to input pins only after the device is
powered-on as described above.
LINEAR REGULATOR
using its output to power external devices is not recom-
mended. External loads can affect the regulator’s sta-
bility and introduce noise into the supply. NXP cannot
guarantee device performance at rated speeds and
temperatures with external loads connected to this
supply.
CURRENT CONSUMPTION BY OPERATING MODE
parameters. To make this data more usable, the values
presented in Table 22 were derived under the condi-
tions presented here.
Maximum Specified Value
determined using these operating characteristics:
• All IP blocks either operating or enabled at maximum
• Core operating at maximum power configuration
• All I/O loads at maximum (50 pF)
• All voltages at maximum specified values
• Maximum specified ambient temperature.
Typical
using a ‘typical’ application under ‘typical’ environmental
conditions and the following operating characteristics:
• SPI, Timer, and UART peripherals operating; all
• LCD enabled with 320 × 240 × 16-bit color, 60 Hz
• I/O loads at nominal
• FCLK = 51.6 MHz; HCLK = 51.6 MHz
• All voltages at typical values
• Nominal case temperature.
Preliminary data sheet
frequency and size configuration
other peripherals disabled
refresh rate
When using an external 1.8 V supply (instead of the
If a longer delay time is needed, the voltage differ-
To avoid a potential latchup condition, voltage
Although this device contains an on-board regulator,
Current consumption can depend on a number of
The values specified in the MAXIMUM column were
The values in the TYPICAL column were determined
NXP Semiconductors
Rev. 01 — 16 July 2007
PERIPHERAL CURRENT CONSUMPTION
23 shows the typical current consumption for each of
the on-board peripheral blocks. The values were deter-
mined with the peripheral clock running at maximum
frequency, typical conditions, and no I/O loads. This
current is supplied by the 1.8 V power supply.
NOTES:
1. ICHIP = Chip Current with Linear Regulator (Core + I/O)
2. ICORE, IIO, IANALOG are the respective current consumption
IANALOG Analog Current
IANALOG Analog Current
IANALOG Analog Current
SYMBOL
ICORE
ICORE
ICORE
ISTOP
ILEAK
ILEAK
ICHIP
ICHIP
ICHIP
In addition to the modal current consumption, Table
specifications for VDDC, VDD, and VDDA.
IIO
IIO
IIO
Table 23. Peripheral Current Consumption
Table 22. Current Consumption by Mode
Counter/Timers
PERIPHERAL
STANDBY MODE (TYPICAL CONDITIONS ONLY)
SLEEP MODE (TYPICAL CONDITIONS ONLY)
UARTs
DMA
Chip Current with Linear Regulator
Core Current without Linear Regulator
I/O Current without Linear Regulator
Core Current with Linear Regulator
Core Current without Linear Regulator
Current drawn by I/O
Core Current with Linear Regulator
Core Current without Linear Regulator
Current drawn by I/O
Core Current with Linear Regulator, I/O,
and 14.7456 MHz osc.
Leakage Current, Core and I/O
Leakage Current, Core and I/O
RTC
SSP
LCD
STOP2 MODE (RTC OFF)
STOP2 MODE (RTC ON)
PARAMETER
ACTIVE MODE
STOP1 MODE
TYPICAL
200
500
200
4.1
2.2
5
LH75401/LH75411
TYP. UNITS
50.2
42.1
42.7
34.6
2.96
400
1.3
0.8
1.3
3.9
2.5
1.2
34
18
5
UNITS
mA
mA
µA
µA
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
µA
39

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