PHKD13N03LT NXP Semiconductors, PHKD13N03LT Datasheet
PHKD13N03LT
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PHKD13N03LT Summary of contents
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... PHKD13N03LT Dual N-channel TrenchMOS logic level FET Rev. 5 — 27 December 2011 1. Product profile 1.1 General description Dual logic level N-channel enhancement mode Field-Effect Transistor (FET plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only. ...
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... °C; see Figure °C sp ≤ 10 µ °C; pulsed All information provided in this document is subject to legal disclaimers. Rev. 5 — 27 December 2011 PHKD13N03LT Graphic symbol Version SOT96-1 Min Max - kΩ ...
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... T (°C) sp Fig All information provided in this document is subject to legal disclaimers. Rev. 5 — 27 December 2011 PHKD13N03LT Dual N-channel TrenchMOS logic level FET 120 der 100 Normalized total power dissipation as a function of solder point temperature t p 100 μ ...
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... Transient thermal impedance from junction to solder point as a function of pulse duration PHKD13N03LT Product data sheet Dual N-channel TrenchMOS logic level FET Conditions see Figure 4 minimum footprint ; mounted on a printed-circuit board - All information provided in this document is subject to legal disclaimers. Rev. 5 — 27 December 2011 PHKD13N03LT Min Typ Max Unit - - 35 K K/W 003aaa415 t ...
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... I = 1.5 A G(ext ° see Figure /dt = -100 A/µ ° All information provided in this document is subject to legal disclaimers. Rev. 5 — 27 December 2011 PHKD13N03LT Min Typ Max 2 ...
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... V 2.5 V 2.4 V 2.3 V 0.6 0 (V) DS Fig 6. 003aaa426 max (V) GS Fig 8. All information provided in this document is subject to legal disclaimers. Rev. 5 — 27 December 2011 PHKD13N03LT Dual N-channel TrenchMOS logic level FET 10 × > DSon 150 ° Transfer characteristics: drain current as a function of gate-source voltage ...
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... Fig 10. Normalized drain-source on-state resistance 003aaa330 (pF (nC) G Fig 12. Input, output and reverse transfer capacitances All information provided in this document is subject to legal disclaimers. Rev. 5 — 27 December 2011 PHKD13N03LT Dual N-channel TrenchMOS logic level FET 2 a 1.5 1 0.5 0 − factor as a function of junction temperature ...
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... PHKD13N03LT Product data sheet ( 150 °C 0 0.2 0.4 0.6 All information provided in this document is subject to legal disclaimers. Rev. 5 — 27 December 2011 PHKD13N03LT Dual N-channel TrenchMOS logic level FET 003aaa329 = 25 ° 0 (V) SD © NXP B.V. 2011. All rights reserved ...
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... REFERENCES JEDEC JEITA MS-012 All information provided in this document is subject to legal disclaimers. Rev. 5 — 27 December 2011 PHKD13N03LT Dual N-channel TrenchMOS logic level FET θ detail ...
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... Product data sheet Dual N-channel TrenchMOS logic level FET Data sheet status Change notice Product data sheet - Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 5 — 27 December 2011 PHKD13N03LT Supersedes PHKD13N03LT v.4 PHKD13N03LT v.3 © NXP B.V. 2011. All rights reserved ...
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... All information provided in this document is subject to legal disclaimers. Rev. 5 — 27 December 2011 PHKD13N03LT Dual N-channel TrenchMOS logic level FET © NXP B.V. 2011. All rights reserved ...
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... TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 5 — 27 December 2011 PHKD13N03LT Dual N-channel TrenchMOS logic level FET Trademarks © NXP B.V. 2011. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 27 December 2011 Document identifier: PHKD13N03LT ...