STM32F205ZG STMicroelectronics, STM32F205ZG Datasheet - Page 51

• Manufacturer Part Number: STM32F205ZG
• Description: High-performance ARM Cortex-M3 MCU with 1 Mbyte Flash, 120 MHz CPU, ART Accelerator
• Manufacturer: STMicroelectronics

Specifications of STM32F205ZG

• 10/100 Ethernet Mac With Dedicated Dma: supports IEEE 1588v2 hardware, MII/RMII

STM32F205xx, STM32F207xx
Table 6.
1. I = input, O = output, S = supply, HiZ = high impedance.
2. FT = 5 V tolerant; TT = 3.6 V tolerant.
3. Function availability depends on the chosen device.
4. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current
5. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after
6. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
7. If the device is delivered in an UFBGA176 package and if the REGOFF pin is set to V
8. FSMC_NL pin is also named FSMC_NADV on memory devices.
9. RFU means “reserved for future use”. This pin can be tied to V
63 D8
64 D9 100 144 172 C5
-
-
-
-
-
-
-
-
(3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: the speed should not exceed 2 MHz with a
maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED).
reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC
register description sections in the STM32F20x and STM32F21x reference manual, available from the STMicroelectronics
website: www.st.com.
as an internal Reset (active low).
C8
-
-
-
-
-
-
-
98 142 170 A3
99 143 171 C6
-
-
-
-
-
-
-
Pins
STM32F20x pin and ball definitions (continued)
-
-
- 173 D4
- 174 C4
- 175 C3
- 176 C2
-
-
-
-
D5
-
-
Pin name
IRROFF
RFU
V
V
PE1
V
PI4
PI5
PI6
PI7
DD_3
SS_3
SS
(9)
Doc ID 15818 Rev 8
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O
S
S
S
DD
(after reset)
function
,V
IRROFF
V
V
SS
Main
PE1
V
PI4
PI5
PI6
PI7
SS_3
DD_3
SS
or left unconnected.
(3)
FSMC_NBL1 / DCMI_D3/
TIM8_BKIN / DCMI_D5/
TIM8_CH2 / DCMI_D6/
TIM8_CH3 / DCMI_D7/
Alternate functions
DD
DCMI_VSYNC/
EVENTOUT
EVENTOUT
TIM8_CH1 /
EVENTOUT
EVENTOUT
EVENTOUT
(Regulator OFF), then PA0 is used
Pinouts and pin description
functions
Other
51/170