ST72324LK2 STMicroelectronics, ST72324LK2 Datasheet - Page 105
ST72324LK2
Manufacturer Part Number
ST72324LK2
Description
3V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
Manufacturer
STMicroelectronics
Datasheet
1.ST72324LK2.pdf
(154 pages)
Specifications of ST72324LK2
Hdflash Endurance
100 cycles, data retention
Clock Sources
crystal/ceramic resonator oscillators, internal RC oscillator, and bypass for external clock
Four Power Saving Modes
Halt, Active-Halt, Wait and Slow
Main Clock Controller With
Real time base, Beep and Clock-out capabilities
16-bit Timer A With
1 input capture, 1 output compare, external clock input, PWM and pulse generator modes
16-bit Timer B With
2 input captures, 2 output compares, PWM and pulse generator modes
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INSTRUCTION SET OVERVIEW (Cont’d)
11.1.1 Inherent
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required informa-
tion for the CPU to process the operation.
11.1.2 Immediate
Immediate instructions have 2 bytes, the first byte
contains the opcode, the second byte contains the
operand value.
NOP
TRAP
WFI
HALT
RET
IRET
SIM
RIM
SCF
RCF
RSP
LD
CLR
PUSH/POP
INC/DEC
TNZ
CPL, NEG
MUL
SLL, SRL, SRA, RLC,
RRC
SWAP
Immediate Instruction
LD
CP
BCP
AND, OR, XOR
ADC, ADD, SUB, SBC
Inherent Instruction
No operation
S/W Interrupt
Wait For Interrupt (Low Pow-
er Mode)
Halt Oscillator (Lowest Power
Mode)
Sub-routine Return
Interrupt Sub-routine Return
Set Interrupt Mask (level 3)
Reset Interrupt Mask (level 0)
Set Carry Flag
Reset Carry Flag
Reset Stack Pointer
Load
Clear
Push/Pop to/from the stack
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Byte Multiplication
Shift and Rotate Operations
Swap Nibbles
Load
Compare
Bit Compare
Logical Operations
Arithmetic Operations
Function
Function
11.1.3 Direct
In Direct instructions, the operands are referenced
by their memory address.
The direct addressing mode consists of two sub-
modes:
Direct (short)
The address is a byte, thus requires only one byte
after the opcode, but only allows 00 - FF address-
ing space.
Direct (long)
The address is a word, thus allowing 64 Kbyte ad-
dressing space, but requires 2 bytes after the op-
code.
11.1.4 Indexed (No Offset, Short, Long)
In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.
The indirect addressing mode consists of three
submodes:
Indexed (No Offset)
There is no offset, (no extra byte after the opcode),
and allows 00 - FF addressing space.
Indexed (Short)
The offset is a byte, thus requires only one byte af-
ter the opcode and allows 00 - 1FE addressing
space.
Indexed (long)
The offset is a word, thus allowing 64 Kbyte ad-
dressing space and requires 2 bytes after the op-
code.
11.1.5 Indirect (Short, Long)
The required data byte to do the operation is found
by its memory address, located in memory (point-
er).
The pointer address follows the opcode. The indi-
rect addressing mode consists of two submodes:
Indirect (short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
Indirect (long)
ST72324Lxx
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