ST72324LS4 STMicroelectronics, ST72324LS4 Datasheet - Page 41
ST72324LS4
Manufacturer Part Number
ST72324LS4
Description
8-bit MCU
Manufacturer
STMicroelectronics
Datasheet
1.ST72324LK2.pdf
(154 pages)
Specifications of ST72324LS4
Hdflash Endurance
100 cycles, data retention
Clock Sources
crystal/ceramic resonator oscillators, internal RC oscillator, and bypass for external clock
Four Power Saving Modes
Halt, Active-Halt, Wait and Slow
Main Clock Controller With
Real time base, Beep and Clock-out capabilities
16-bit Timer A With
1 input capture, 1 output compare, external clock input, PWM and pulse generator modes
16-bit Timer B With
2 input captures, 2 output compares, PWM and pulse generator modes
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I/O PORTS (Cont’d)
Figure 26. I/O Port General Block Diagram
Table 11. I/O Port Mode Options
Legend: NI - not implemented
Input
Output
REGISTER
ACCESS
SOURCE (ei
EXTERNAL
INTERRUPT
DDR SEL
Off - implemented not activated
On - implemented and activated
OR SEL
DR SEL
Floating with/without Interrupt
Pull-up with/without Interrupt
Push-pull
Open Drain (logic level)
True Open Drain
DDR
Configuration Mode
x
DR
OR
)
ALTERNATE
OUTPUT
ALTERNATE
ENABLE
If implemented
1
0
1
0
Pull-Up
Off
On
Off
NI
Note: The diode to V
true open drain pads. A local protection between
the pad and V
vice against positive stress.
N-BUFFER
PULL-UP
CONDITION
P-Buffer
Off
On
Off
NI
SS
SCHMITT
TRIGGER
CMOS
is implemented to protect the de-
V
DD
DD
NI (see note)
to V
is not implemented in the
On
P-BUFFER
(see table below)
DD
V
Diodes
DD
DIODES
(see table below)
PULL-UP
(see table below)
ALTERNATE
ST72324Lxx
ANALOG
INPUT
to V
INPUT
PAD
On
SS
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