ST72345C4 STMicroelectronics, ST72345C4 Datasheet - Page 56

• Manufacturer Part Number: ST72345C4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72345C4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

Interrupts
8.3
Note:
8.4
56/247
Interrupts and low-power modes
All interrupts allow the processor to exit the Wait low-power mode. On the contrary, only
external and other specified interrupts allow the processor to exit from the Halt modes (see
column “Exit from Halt” in “Interrupt Mapping” table). When several pending interrupts are
present while exiting Halt mode, the first one serviced can only be an interrupt with exit from
Halt mode capability and it is selected through the same decision process shown in
Figure
If an interrupt, that is not able to Exit from Halt mode, is pending with the highest priority
when exiting Halt mode, this interrupt is serviced after the first one serviced.
Concurrent & nested management
The following
first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the
nested mode in
lowest to the highest: MAIN, IT4, IT3, IT2, IT1, IT0, TLI. The software priority is given for
each interrupt.
Figure 22. Concurrent interrupt management
Warning:
21.
11 / 10
MAIN
RIM
Figure 22
Figure
A stack overflow may occur without notifying the software of
the failure.
IT2
23. The interrupt hardware priority is given in this order from the
and
Figure 23
IT1
Doc ID 12321 Rev 5
TRAP
show two different interrupt management modes. The
IT1
IT0
IT3
IT4
10
SOFTWARE
PRIORITY
LEVEL
MAIN
ST72344xx ST72345xx
3
3
3
3
3
3
3/0
I1
1 1
1 1
1 1
1 1
1 1
1 1
I0