STM6524 STMicroelectronics, STM6524 Datasheet - Page 5

• Manufacturer Part Number: STM6524
• Description: 6-pin Smart Reset
• Manufacturer: STMicroelectronics

Specifications of STM6524

• Option 1: fully push-button controlled, no fixed or minimum pulse width guaranteed
• Option 2: defined output reset pulse duration (tREC), factory-programmed
• Operating Temperature: –40 °C to +85 °C
• Udfn6 Package: 1.6 mm x 1.3 mm

Description
1
Customer test mode
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Description
The Smart Reset™ devices provide a useful feature that ensures inadvertent short reset
push-button closures do not cause system resets. This is done by implementing extended
Smart Reset™ input delay time (t
ensures a safe reset and eliminates the need for a specific dedicated reset button.
This reset configuration provides versatility and allows the application to distinguish between
a software generated interrupt and a hard system reset. When the input push-buttons are
connected to microcontroller interrupt inputs, and are closed for a short time, the processor
can only be interrupted. If the system still does not respond properly, continuing to keep the
push-buttons closed for the extended setup time t
through the reset output.
The STM6524 has two combined delayed Smart Reset™ inputs (SR0, SR1) with preset
delayed Smart Reset™ setup time (t
Smart Reset™ inputs were held active for the selected t
selected option the RST output remains asserted either until at least one SR input goes to
inactive logic level (i.e. neither fixed nor minimum reset pulse width is set) or the output reset
pulse duration is fixed for t
active-low or active-high, push-pull or open-drain with optional pull-up resistor. The device
fully operates over a broad V
ignored and outputs are deasserted; the deasserted reset output levels are then valid down
to 1.0 V.
After pull of SR0 up to V
shorten t
t
option is not used). This is a feedback and a user knows that the device is locked in the test
mode. Each time both SR inputs are connected to ground in test mode a shorten
t
mode is possible by a new startup of the device (i.e. V
state). In this way the device can be quickly tested without repeating test mode triggering.
Advantage of this solution is pretty high glitch immunity, feedback to user about entry to the
test mode and testability within full V
REC
SRC-SHORT
(if t
REC
SRC-INI
(21 ms, typ.) is used instead of long t
option is used) or stays low as long as overvoltage on SR0 in detected (if t
(42 ms, typ.). After t
TEST
REC
CC
or more (V
Doc ID 022335 Rev 1
(i.e. factory-programmed). The reset output, RST, is
range 1.65 V to 5.5 V. Below 1.575 V typ. the inputs are
SRC
SRC-INI
SRC
CC
) and combined push-button inputs, which together
range.
). The reset output is asserted after both of the
CC
expires, the RST output either goes down for
+ 1.4 V, max.) we start counting initial
SRC
SRC
(0.5 s -10 s). Return from to normal
CC
causes a hard reset of the processor
SRC
goes to 0 V and back to its original
delay time. Depending on
STM6524
REC