DS2431-A1 Maxim, DS2431-A1 Datasheet
DS2431-A1
Related parts for DS2431-A1
DS2431-A1 Summary of contents
Page 1
... General Description The DS2431- AEC-Q100 Grade 1 qualified ver- sion of the DS2431. The logical behavior of both ver- sions is identical. The DS2431- 1024-bit, 1-Wire EEPROM chip organized as four memory pages of 256 bits each. Data is written to an 8-byte scratchpad, veri- fied, and then copied to the EEPROM memory ...
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... Operating Temperature Range .........................-40°C to +125°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
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... Note 12: Applies to a single device attached to a 1-Wire line. Note 13: The earliest recognition of a negative edge is possible at t Note 14: Defines maximum possible bit rate. Equal to t Note 15: Interval after t during which a bus master is guaranteed to sample a logic 0 on I/O if there is a DS2431-A1 present. RSTL Minimum limit maximum limit is t PDHMAX Note 16: ε ...
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... The DS2431-A1 combines 1024 bits of EEPROM, an 8-byte register/control page with up to seven user read/write bytes, and a fully featured 1-Wire interface in a single chip. Each DS2431-A1 has its own 64-bit ROM registration number that is factory lasered into the chip to provide a guaranteed unique identity for absolute traceability ...
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... READ MEMORY DATA MEMORY, REGISTER PAGE 48-BIT SERIAL NUMBER Each DS2431-A1 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last 8 bits are a CRC (cyclic redundancy check) of the first 56 bits. ...
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... Data memory and registers are located in a linear address space, as shown in Figure 5. The data memory and the registers have unrestricted read access. The DS2431-A1 EEPROM array consists of 18 rows of 8 bytes each. The first 16 rows are divided equally into four memory pages (32 bytes each). These four pages are the primary data memory ...
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... The DS2431-A1 employs three address registers: TA1, TA2, and E/S (Figure 6). These registers are common to many other 1-Wire devices but operate slightly different- ly with the DS2431-A1. Registers TA1 and TA2 must be loaded with the target address to which the data is writ- ten or from which data is read. Register E read- only transfer-status register used to verify data integrity with write commands ...
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... Memory Function Commands The Memory Function Flow Chart (Figure 7) describes the protocols necessary for accessing the memory of the DS2431-A1. An example on how to use these func- tions to write to and read from the device is included at the end of this document. 8 _______________________________________________________________________________________ ...
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... LOADS THE BITWISE LOGICAL AND, THE TRANSMITTED BYTE, AND THE DATA BYTE FROM THE TARGETED N BUS MASTER Rx CRC-16 ADDRESS INTO OF COMMAND, ADDRESS, THE SP. E/S BYTE, DATA BYTES AS SENT BY THE DS2431-A1 N BUS MASTER MASTER Tx RESET? Rx "1"s TO FIGURE 7 AAh 2ND PART E2:E0? ...
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... DATA TO ADDRESS DS2431 Tx "0" BUS MASTER Rx "1"s Y MASTER Tx RESET? N DS2431 Tx "1" N MASTER Tx RESET 1-Wire IDLE HIGH FOR POWER DS2431-A1 SETS MEMORY ADDRESS = (T15:T0) BUS MASTER Rx DATA BYTE FROM MEMORY ADDRESS Y BUS MASTER MASTER Tx RESET? Rx "1" MASTER Tx RESET? Y ADDRESS < ...
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... Automotive Applications The 1-Wire bus is a system that has a single bus mas- ter and one or more slaves. In all instances the DS2431- slave device. The bus master is typical microcontroller. The discussion of this bus system is broken down into three topics: hardware configura- tion, transaction sequence, and 1-Wire signaling (signal types and timing) ...
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... The presence pulse lets the bus master know that the DS2431- the bus and is ready to operate. For more details, see the 1-Wire Signaling section. 1-Wire ROM Function ...
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... N SEARCH ROM SKIP ROM COMMAND? COMMAND DS2431-A1 Tx BIT 0 DS2431-A1 Tx BIT 0 MASTER Tx BIT BIT 0 MATCH? Y DS2431-A1 Tx BIT 1 DS2431-A1 Tx BIT 1 MASTER Tx BIT BIT 1 MATCH? Y DS2431-A1 Tx BIT 63 DS2431-A1 Tx BIT 63 MASTER Tx BIT BIT 63 MATCH MEMORY FUNCTIONS FLOW CHART (FIGURE 7) ...
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... Figure 10 shows the initialization sequence required to begin any communication with the DS2431-A1. A reset pulse followed by a presence pulse indicates that the DS2431-A1 is ready to receive data, given the correct ROM and memory function command. If the bus master uses slew-rate control on the falling edge, it must pull ...
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... When responding with a 1, the DS2431-A1 does not hold the data line low at all, and the voltage starts rising as soon δ (rise time) on one side and the inter- ...
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... WRITE-ZERO TIME SLOT V PUP V IHMASTER ILMAX RESISTOR READ-DATA TIME SLOT PUP V IHMASTER ILMAX RESISTOR Figure 11. Read/Write Timing Diagrams 16 ______________________________________________________________________________________ ε t SLOT MASTER t W0L t SLOT MASTER t MSR MASTER SAMPLING WINDOW δ t SLOT MASTER ε t REC t REC DS2431-A1 ...
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... In contrast to the 8-bit CRC, the 16-bit CRC is always communicated in the inverted form. A CRC generator inside the DS2431-A1 chip (Figure 13) calculates a new 16-bit CRC, as shown in the command flow chart (Figure 7). The bus master compares the CRC value ...
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... STAGE STAGE they were sent by the DS2431-A1. The DS2431-A1 transmits this CRC only if the reading continues through the end of the scratchpad. For more information on generating CRC values, refer to Application Note 27 . DESCRIPTION 6TH 7TH 8TH STAGE STAGE STAGE ...
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Command-Specific 1-Wire Communication Protocol—Color Codes Master to Slave Slave to Master Write Scratchpad RST PD Select WS TA <8–T2:T0 bytes> CRC-16 FF Loop Read Scratchpad RST PD Select RS TA-E/S <8–T2:T0 bytes> CRC-16 FF Loop Copy Scratchpad (Success) RST PD ...
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... For the latest package outline information and land patterns www.maxim-ic.com/packages. PACKAGE TYPE 6 TSOC 20 ______________________________________________________________________________________ With only a single DS2431-A1 connected to the bus master, the communication looks like this: DATA (LSB FIRST) (Reset) Reset pulse (Presence) Presence pulse CCh Issue “Skip ROM” command 0Fh Issue “ ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21 © ...